公开(公告)号：US11812542B2

公开(公告)日：2023-11-07

申请号：US18104956

申请日：2023-02-02

Applicant: TDK CORPORATION

Inventor： Shuichi Takizawa ,  Hironori Sato ,  Atsushi Yoshino ,  Hideki Kachi

IPC: H05K5/06 ,  H05K9/00 ,  H05K1/18

CPC classification number: H05K9/0045 ,  H05K1/181 ,  H05K5/065

Abstract: A circuit module 2 comprises: a wiring structure 4; at least one electronic component 6a, 6b arranged on the upper surface of the wiring structure 4; an insulating resin layer 8 which is provided on the upper surface of the wiring structure 4 and in which at least one electronic component 6a, 6b is embedded; and a metal layer 10 provided on the upper surface of the insulating resin layer 8. The surface roughness of the portion S1 directly above each electronic component on the upper surface of the insulating resin layer 8 is expressed as R1. The surface roughness of the portion S2 other than the portion directly above all the electronic components on the upper surface of the insulating resin layer 8 is expressed as R2. At least one R1 satisfies the condition: R1>R2.

公开(公告)号：US11076513B2

公开(公告)日：2021-07-27

申请号：US16284231

申请日：2019-02-25

Applicant: TDK CORPORATION

Inventor： Shuichi Takizawa ,  Hironori Sato ,  Atsushi Yoshino ,  Hideki Kachi

IPC: H05K9/00 ,  H01L23/552 ,  H01L23/00 ,  H05K5/06 ,  H05K1/18 ,  H01L23/31 ,  H01L23/29

Abstract: A circuit module 2 comprises: a wiring structure 4; at least one electronic component 6a, 6b arranged on the upper surface of the wiring structure 4; an insulating resin layer 8 which is provided on the upper surface of the wiring structure 4 and in which at least one electronic component 6a, 6b is embedded; and a metal layer 10 provided on the upper surface of the insulating resin layer 8. The surface roughness of the portion S1 directly above each electronic component on the upper surface of the insulating resin layer 8 is expressed as R1. The surface roughness of the portion S2 other than the portion directly above all the electronic components on the upper surface of the insulating resin layer 8 is expressed as R2. At least one R1 satisfies the condition: R1>R2.

公开(公告)号：US11979988B2

公开(公告)日：2024-05-07

申请号：US17671119

申请日：2022-02-14

Applicant: TDK CORPORATION

Inventor： Shuichi Takizawa ,  Atsushi Yoshino ,  Yuki Okino ,  Hiromu Harada

IPC: H05K1/14 ,  H05K1/18 ,  H05K3/28 ,  H05K3/36

CPC classification number: H05K1/141 ,  H05K1/181 ,  H05K3/284 ,  H05K3/368

Abstract: Disclosed herein is an electric circuit module that includes a circuit board, an electronic component mounted on an upper surface of the circuit board, and a mold member that covers the upper and side surfaces of the circuit board. The lower area of the side surface of the circuit board is exposed so as not to be covered with the mold member.

公开(公告)号：US11606888B2

公开(公告)日：2023-03-14

申请号：US17352982

申请日：2021-06-21

Applicant: TDK CORPORATION

Inventor： Shuichi Takizawa ,  Hironori Sato ,  Atsushi Yoshino ,  Hideki Kachi

IPC: H05K5/06 ,  H05K9/00 ,  H05K1/18

Abstract: A circuit module 2 comprises: a wiring structure 4; at least one electronic component 6a, 6b arranged on the upper surface of the wiring structure 4; an insulating resin layer 8 which is provided on the upper surface of the wiring structure 4 and in which at least one electronic component 6a, 6b is embedded; and a metal layer 10 provided on the upper surface of the insulating resin layer 8. The surface roughness of the portion S1 directly above each electronic component on the upper surface of the insulating resin layer 8 is expressed as R1. The surface roughness of the portion S2 other than the portion directly above all the electronic components on the upper surface of the insulating resin layer 8 is expressed as R2. At least one R1 satisfies the condition: R1>R2.

公开(公告)号：US10797003B2

公开(公告)日：2020-10-06

申请号：US16284457

申请日：2019-02-25

Applicant: TDK Corporation

Inventor： Shuichi Takizawa ,  Hironori Sato ,  Atsushi Yoshino

IPC: H01L23/552 ,  H03H9/02 ,  H01G4/30 ,  H01G4/12 ,  H01G2/22

Abstract: A circuit module 2 comprises: a wiring structure 4; an electronic component 6a, 6b arranged on the upper surface of the wiring structure 4; an insulating resin layer 8 which is provided on the upper surface of the wiring structure 4 and in which the electronic component 6a, 6b is embedded; and a metal layer 10 provided on a side surface S1 of the insulating resin layer 8 and a side surface S2 of the wiring structure 4. The surface roughness of the side surface S1 of the insulating resin layer 8 is expressed as R1. The surface roughness of the side surface S2 of the wiring structure 4 is expressed as R2. R1 and R2 differ from each other.