公开(公告)号：US11979988B2

公开(公告)日：2024-05-07

申请号：US17671119

申请日：2022-02-14

Applicant: TDK CORPORATION

Inventor： Shuichi Takizawa ,  Atsushi Yoshino ,  Yuki Okino ,  Hiromu Harada

IPC: H05K1/14 ,  H05K1/18 ,  H05K3/28 ,  H05K3/36

CPC classification number: H05K1/141 ,  H05K1/181 ,  H05K3/284 ,  H05K3/368

Abstract: Disclosed herein is an electric circuit module that includes a circuit board, an electronic component mounted on an upper surface of the circuit board, and a mold member that covers the upper and side surfaces of the circuit board. The lower area of the side surface of the circuit board is exposed so as not to be covered with the mold member.

公开(公告)号：US11606888B2

公开(公告)日：2023-03-14

申请号：US17352982

申请日：2021-06-21

Applicant: TDK CORPORATION

Inventor： Shuichi Takizawa ,  Hironori Sato ,  Atsushi Yoshino ,  Hideki Kachi

IPC: H05K5/06 ,  H05K9/00 ,  H05K1/18

Abstract: A circuit module 2 comprises: a wiring structure 4; at least one electronic component 6a, 6b arranged on the upper surface of the wiring structure 4; an insulating resin layer 8 which is provided on the upper surface of the wiring structure 4 and in which at least one electronic component 6a, 6b is embedded; and a metal layer 10 provided on the upper surface of the insulating resin layer 8. The surface roughness of the portion S1 directly above each electronic component on the upper surface of the insulating resin layer 8 is expressed as R1. The surface roughness of the portion S2 other than the portion directly above all the electronic components on the upper surface of the insulating resin layer 8 is expressed as R2. At least one R1 satisfies the condition: R1>R2.

公开(公告)号：US10797003B2

公开(公告)日：2020-10-06

申请号：US16284457

申请日：2019-02-25

Applicant: TDK Corporation

Inventor： Shuichi Takizawa ,  Hironori Sato ,  Atsushi Yoshino

IPC: H01L23/552 ,  H03H9/02 ,  H01G4/30 ,  H01G4/12 ,  H01G2/22

Abstract: A circuit module 2 comprises: a wiring structure 4; an electronic component 6a, 6b arranged on the upper surface of the wiring structure 4; an insulating resin layer 8 which is provided on the upper surface of the wiring structure 4 and in which the electronic component 6a, 6b is embedded; and a metal layer 10 provided on a side surface S1 of the insulating resin layer 8 and a side surface S2 of the wiring structure 4. The surface roughness of the side surface S1 of the insulating resin layer 8 is expressed as R1. The surface roughness of the side surface S2 of the wiring structure 4 is expressed as R2. R1 and R2 differ from each other.

公开(公告)号：US20140153196A1

公开(公告)日：2014-06-05

申请号：US14091056

申请日：2013-11-26

Applicant: TDK Corporation

Inventor： Shuichi Takizawa ,  Kenichi Kawabata

IPC: H05K1/18

CPC classification number: H05K1/181 ,  H05K3/284 ,  H05K3/3442 ,  H05K3/3452 ,  H05K2201/09118 ,  H05K2201/099 ,  Y02P70/611

Abstract: An electronic module is provided with a circuit board 2, a chip component 3 surface-mounted on the circuit board 2 and a mold member 4 that seals the chip component 3. The circuit board 2 includes a land 7 and a resist pattern 8A that partially covers the land 7. The chip component 3 has a bottom electrode 6b and a side electrode 6c. The resist pattern 8A has an overlapped portion overlapped with the bottom electrode 6b of the chip component 3 in a planar view. A portion of the mold member 4 is filled at least in a first gap D1 between the resist pattern 8A and the first solder portion 10a.

Abstract translation: 电子模块设置有电路板2，表面安装在电路板2上的芯片部件3和密封芯片部件3的模具部件4.电路板2包括焊盘7和抗蚀剂图案8A，其部分地 芯片部件3具有底部电极6b和侧面电极6c。 抗蚀剂图案8A在平面图中具有与芯片部件3的底部电极6b重叠的重叠部分。 至少在抗蚀剂图案8A和第一焊料部分10a之间的第一间隙D1中填充模具构件4的一部分。

公开(公告)号：US11812542B2

公开(公告)日：2023-11-07

申请号：US18104956

申请日：2023-02-02

Applicant: TDK CORPORATION

Inventor： Shuichi Takizawa ,  Hironori Sato ,  Atsushi Yoshino ,  Hideki Kachi

IPC: H05K5/06 ,  H05K9/00 ,  H05K1/18

CPC classification number: H05K9/0045 ,  H05K1/181 ,  H05K5/065

Abstract: A circuit module 2 comprises: a wiring structure 4; at least one electronic component 6a, 6b arranged on the upper surface of the wiring structure 4; an insulating resin layer 8 which is provided on the upper surface of the wiring structure 4 and in which at least one electronic component 6a, 6b is embedded; and a metal layer 10 provided on the upper surface of the insulating resin layer 8. The surface roughness of the portion S1 directly above each electronic component on the upper surface of the insulating resin layer 8 is expressed as R1. The surface roughness of the portion S2 other than the portion directly above all the electronic components on the upper surface of the insulating resin layer 8 is expressed as R2. At least one R1 satisfies the condition: R1>R2.

公开(公告)号：US09439288B2

公开(公告)日：2016-09-06

申请号：US14091056

申请日：2013-11-26

Applicant: TDK Corporation

Inventor： Shuichi Takizawa ,  Kenichi Kawabata

IPC: H05K7/00 ,  H05K1/18 ,  H05K3/28 ,  H05K3/34

CPC classification number: H05K1/181 ,  H05K3/284 ,  H05K3/3442 ,  H05K3/3452 ,  H05K2201/09118 ,  H05K2201/099 ,  Y02P70/611

Abstract: An electronic module is provided with a circuit board 2, a chip component 3 surface-mounted on the circuit board 2 and a mold member 4 that seals the chip component 3. The circuit board 2 includes a land 7 and a resist pattern 8A that partially covers the land 7. The chip component 3 has a bottom electrode 6b and a side electrode 6c. The resist pattern 8A has an overlapped portion overlapped with the bottom electrode 6b of the chip component 3 in a planar view. A portion of the mold member 4 is filled at least in a first gap D1 between the resist pattern 8A and the first solder portion 10a.

Abstract translation: 电子模块设置有电路板2，表面安装在电路板2上的芯片部件3和密封芯片部件3的模具部件4.电路板2包括焊盘7和抗蚀剂图案8A，其部分地 芯片部件3具有底部电极6b和侧面电极6c。 抗蚀剂图案8A在平面图中具有与芯片部件3的底部电极6b重叠的重叠部分。 至少在抗蚀剂图案8A和第一焊料部分10a之间的第一间隙D1中填充模具构件4的一部分。

公开(公告)号：US11076513B2

公开(公告)日：2021-07-27

申请号：US16284231

申请日：2019-02-25

Applicant: TDK CORPORATION

Inventor： Shuichi Takizawa ,  Hironori Sato ,  Atsushi Yoshino ,  Hideki Kachi

IPC: H05K9/00 ,  H01L23/552 ,  H01L23/00 ,  H05K5/06 ,  H05K1/18 ,  H01L23/31 ,  H01L23/29

Abstract: A circuit module 2 comprises: a wiring structure 4; at least one electronic component 6a, 6b arranged on the upper surface of the wiring structure 4; an insulating resin layer 8 which is provided on the upper surface of the wiring structure 4 and in which at least one electronic component 6a, 6b is embedded; and a metal layer 10 provided on the upper surface of the insulating resin layer 8. The surface roughness of the portion S1 directly above each electronic component on the upper surface of the insulating resin layer 8 is expressed as R1. The surface roughness of the portion S2 other than the portion directly above all the electronic components on the upper surface of the insulating resin layer 8 is expressed as R2. At least one R1 satisfies the condition: R1>R2.