公开(公告)号：US11222817B2

公开(公告)日：2022-01-11

申请号：US16835056

申请日：2020-03-30

申请人： Tessera, Inc.

发明人： Daniel C. Edelstein ,  Chih-Chao Yang

IPC分类号： H01L23/52 ,  H01L21/768 ,  H01L23/532 ,  H01L21/02 ,  H01L23/528 ,  H01L21/288

摘要： A device relates to a semiconductor device. The semiconductor device includes a narrow-line bamboo microstructure integrated within a metal layer of the semiconductor device and a narrow-line polycrystalline microstructure. The narrow-line polycrystalline microstructure is integrated within the same metal layer as the narrow-line bamboo microstructure.

公开(公告)号：US20200328156A1

公开(公告)日：2020-10-15

申请号：US16888245

申请日：2020-05-29

申请人： Tessera, Inc.

发明人： Benjamin D. Briggs ,  Elbert Huang ,  Raghuveer R. Patlolla ,  Cornelius Brown Peethala ,  David L. Rath ,  Chih-Chao Yang

IPC分类号： H01L23/528 ,  H01L23/522 ,  H01L23/532 ,  H01L21/768

摘要： A low aspect ratio interconnect is provided and includes a metallization layer, a liner and a metallic interconnect. The metallization layer includes bottommost and uppermost surfaces. The uppermost surface has a maximum post-deposition height from the bottommost surface at first metallization layer portions. The metallization layer defines a trench at second metallization layer portions. The liner includes is disposed to line the trench and includes liner sidewalls that have terminal edges that extend to the maximum post-deposition height and lie coplanar with the uppermost surface at the first metallization layer portions. The metallic interconnect is disposed on the liner to fill a trench remainder and has an uppermost interconnect surface that extends to the maximum post-deposition height and lies coplanar with the uppermost surface at the first metallization layer portions.

公开(公告)号：US20220165620A1

公开(公告)日：2022-05-26

申请号：US17546511

申请日：2021-12-09

申请人： Tessera, Inc.

发明人： Daniel C. Edelstein ,  Chih-Chao Yang

IPC分类号： H01L21/768 ,  H01L23/532 ,  H01L21/02 ,  H01L23/528

摘要： A device relates to a semiconductor device. The semiconductor device includes a narrow-line bamboo microstructure integrated within a metal layer of the semiconductor device and a narrow-line polycrystalline microstructure. The narrow-line polycrystalline microstructure is integrated within the same metal layer as the narrow-line bamboo microstructure.

公开(公告)号：US20210183699A1

公开(公告)日：2021-06-17

申请号：US17187390

申请日：2021-02-26

申请人： Tessera, Inc.

发明人： Conal E. Murray ,  Chih-Chao Yang

IPC分类号： H01L21/768 ,  H01L23/532 ,  H01L23/522 ,  H01L23/528 ,  C23F4/00 ,  C23F1/44

摘要： A semiconductor interconnect structure having a first electrically conductive structure having a plurality of bottom portions; a dielectric capping layer, at least a portion of the dielectric capping layer being in contact with a first bottom portion of the plurality of bottom portions; and a second electrically conductive structure in electrical contact with a second bottom portion of the plurality of bottom portions. A method of forming the interconnect structure is also provided.

公开(公告)号：US10672707B2

公开(公告)日：2020-06-02

申请号：US16250351

申请日：2019-01-17

申请人： TESSERA, INC.

发明人： Benjamin D. Briggs ,  Elbert E. Huang ,  Raghuveer R. Patlolla ,  Cornelius Brown Peethala ,  David L. Rath ,  Chih-Chao Yang

IPC分类号： H01L23/528 ,  H01L23/522 ,  H01L23/532 ,  H01L21/768

摘要： A low aspect ratio interconnect is provided and includes a metallization layer, a liner and a metallic interconnect. The metallization layer includes bottommost and uppermost surfaces. The uppermost surface has a maximum post-deposition height from the bottommost surface at first metallization layer portions. The metallization layer defines a trench at second metallization layer portions. The liner includes is disposed to line the trench and includes liner sidewalls that have terminal edges that extend to the maximum post-deposition height and lie coplanar with the uppermost surface at the first metallization layer portions. The metallic interconnect is disposed on the liner to fill a trench remainder and has an uppermost interconnect surface that extends to the maximum post-deposition height and lies coplanar with the uppermost surface at the first metallization layer portions.

公开(公告)号：US10804147B2

公开(公告)日：2020-10-13

申请号：US16689142

申请日：2019-11-20

申请人： TESSERA, INC.

发明人： Conal E. Murray ,  Chih-Chao Yang

IPC分类号： H01L21/768 ,  H01L23/532 ,  H01L23/522 ,  H01L23/528 ,  C23F4/00 ,  C23F1/44

摘要： A semiconductor interconnect structure that has a first portion included in an upper interconnect level and a second portion included in a lower interconnect level. The semiconductor interconnect structure has a segment of dielectric capping material that is in contact with the bottom of the first portion, which separates, in part, the upper interconnect level from a lower interconnect level. The second portion is in electrical contact with the first portion.

公开(公告)号：US20200227317A1

公开(公告)日：2020-07-16

申请号：US16835056

申请日：2020-03-30

申请人： Tessera, Inc.

发明人： Daniel C. Edelstein ,  Chih-Chao Yang

IPC分类号： H01L21/768 ,  H01L23/532 ,  H01L21/02 ,  H01L23/528

摘要： A device relates to a semiconductor device. The semiconductor device includes a narrow-line bamboo microstructure integrated within a metal layer of the semiconductor device and a narrow-line polycrystalline microstructure. The narrow-line polycrystalline microstructure is integrated within the same metal layer as the narrow-line bamboo microstructure.

公开(公告)号：US11222815B2

公开(公告)日：2022-01-11

申请号：US16689223

申请日：2019-11-20

申请人： TESSERA, INC.

发明人： Conal E. Murray ,  Chih-Chao Yang

IPC分类号： H01L21/768 ,  H01L23/532 ,  H01L23/522 ,  H01L23/528 ,  C23F4/00 ,  C23F1/44

摘要： A semiconductor interconnect structure having a first electrically conductive structure having a plurality of bottom portions; a dielectric capping layer, at least a portion of the dielectric capping layer being in contact with a first bottom portion of the plurality of bottom portions; and a second electrically conductive structure in electrical contact with a second bottom portion of the plurality of bottom portions. A method of forming the interconnect structure is also provided.