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    Process for fabricating integrated circuit having matched complementary transistors
    1.
    发明授权
    Process for fabricating integrated circuit having matched complementary transistors 失效
    用于制造具有匹配补偿晶体管的集成电路的工艺

    公开(公告)号：US3682724A

    公开(公告)日：1972-08-08

    申请号：US3682724D

    申请日：1969-02-05

    Applicant: TEXAS INSTRUMENTS INC

    Inventor： BOHANNON RALPH O JR

    IPC: H01L21/761 ,  H01L27/06 ,  H01L27/082 ,  H01L7/36 ,  H01L19/00

    CPC classification number: H01L27/0652 ,  H01L21/761 ,  H01L27/0826 ,  Y10S148/085 ,  Y10S148/151

    Abstract: A PROCESS FOR FABRICATING AN INTERGRATED CIRCUIT HAVING A MATCHED PAIR OF COMPLEMENTARY TRANSISTORS, AND DIFTERENT RESISTORS, DIODES AND CAPACITORS. THE STARTING MATERIAL IS A P-TYPE SUBSTRATE WITH AN N-TYPE EPITAZIAL LAYER. FIRST THE COLLECTOR REGION FOTHE PNP TRANSISTOR IS PARTIALLY DIFFUSED, THEN P-TYPE ISOLATION RINGS DIFFUSED AROUND BOTH TRANSISTORS AND THROUGH THE EPITAZIAL LAYER. THEN A THIRD P-TYPE DIFFUSION IS MADE TO FORM THE BASE REGION OF THE NPN TRANSISTOR, A FIRST N-TYPE DIFFUSION IS MADE TO FORM THE BASE REGION FOTHE PNP TRANSISTOR, A SECOND N-TYPE DEPOSITION IS MADE TO FORM THE EMITTER REGION OF THE NPN TRANSISTOR AND BASE CONTACT OF THE PNP TRANSISTOR, AND FINALLY A FOURTH P-TYPE DIFFUSION IS MADE TO FORM THE EMITTER OF THE PNP TRANSISTOR AND THE BASE CONTACT OF THE NPN TRANSISTOR. THE PRODUCT IS AN INTERGRATED CIRCUIT WHEREIN EACH INDIVIDUAL COMPONENT IS ISOLATED AND THE TWO TRANSISTORS HAVE SUBSTANTIALLY THE SAME OPERATIONAL PARAMETERS. A SEPARATE RESISTOR DIFFUSION IS MADE PRIOR TO THE EMITTER DIFFUSION TO ACHIEVE A HIGH SHEET RESISTANCE.

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