公开(公告)号：US3921282A

公开(公告)日：1975-11-25

申请号：US11542871

申请日：1971-02-16

Applicant: TEXAS INSTRUMENTS INC

Inventor： CUNNINGHAM JAMES A ,  WAKEFIELD JR ROBERT H ,  GUIDRY JR MARK R

IPC: H01L21/00 ,  H01L21/762 ,  H01L21/768 ,  H01L23/535 ,  B01J17/00

CPC classification number: H01L23/535 ,  H01L21/00 ,  H01L21/762 ,  H01L21/76213 ,  H01L21/76838 ,  H01L2924/0002 ,  Y10S148/117 ,  Y10S148/122 ,  Y10S148/151 ,  Y10S438/981 ,  H01L2924/00

Abstract: Insulated gate field effect transistor circuits utilizing transistors having a self-aligned gate, reduced parasitic capacitance and lower surface step-heights are fabricated with three levels of interconnects. The self-aligned gate transistors are fabricated with the use of a silicon nitride diffusion mask which also serves as an oxidation barrier in the formation of a thick oxide over the source and drain regions. Diffused interconnects are formed simultaneously with the source and drain region diffusions. The silicon nitride is then replaced with a more suitable dielectric, followed by the formation of polycrystalline silicon interconnects to provide source, drain and gate electrodes, and to provide a second level of interconnects which cross over the diffused interconnects at desired locations. An insulating layer is formed over the silicon interconnects and a metallization interconnect pattern, which crosses over the silicon interconnects at various desired locations is then formed to complete the circuit.

Abstract translation: 采用具有自对准栅极，降低的寄生电容和较低表面阶跃高度的晶体管的绝缘栅场效应晶体管电路用三级互连制造。 使用氮化硅扩散掩模制造自对准栅极晶体管，氮化硅扩散掩模也用作在源极和漏极区域上形成厚氧化物的氧化屏障。 扩散互连与源区和漏区扩散同时形成。 然后用更合适的电介质代替氮化硅，随后形成多晶硅互连以提供源极，漏极和栅电极，并提供在期望位置上跨越扩散互连的第二级互连。 在硅互连上形成绝缘层，然后形成在各种所需位置上穿过硅互连的金属化互连图案以完成电路。