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    Sputtered multilayer ohmic molygold contacts for semiconductor devices
    1.
    发明授权
    Sputtered multilayer ohmic molygold contacts for semiconductor devices 失效
    用于半导体器件的溅射多层次OHMIC MOLYGOLD接触

    公开(公告)号：US3616401A

    公开(公告)日：1971-10-26

    申请号：US3616401D

    申请日：1966-06-30

    Applicant: TEXAS INSTRUMENTS INC

    Inventor： CUNNINGHAM JAMES A ,  ORR COY D

    IPC: H01L21/00 ,  H01L23/485 ,  H01L23/522 ,  H01L27/00 ,  C23C15/00

    CPC classification number: H01L23/522 ,  H01L21/00 ,  H01L23/485 ,  H01L27/00 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Disclosed are methods for depositing multilayer ohmic contacts upon a substrate of semiconductor material disposed within a low pressure chamber; such including for example the particular features of upward sputtering of the various metal films including deposition of a thin layer of molybdenum directly on initially formed integral areas of platinum silicide, followed by simultaneous sputtering of platinum with gold utilizing a sputtering cathode composed of platinum and gold, with the addition of hydrogen into an inert sputtering atmosphere to eliminate undesireable formation of oxides. This invention provides improved adhesion of the sputtered metal films to the semiconductor surface and the silicon oxide, and provides the formation of the metal film which is substantially free of pin holes and which has substantially uniform resistivity.

    Rf sputtering method
    3.
    发明授权
    Rf sputtering method 失效
    射频射频方法

    公开(公告)号：US3677924A

    公开(公告)日：1972-07-18

    申请号：US3677924D

    申请日：1970-03-13

    Applicant: TEXAS INSTRUMENTS INC

    Inventor： CASH JOHN H JR ,  CUNNINGHAM JAMES A

    IPC: C23C14/28 ,  H01J37/34 ,  H01L21/00 ,  H01L23/29 ,  C23C15/00

    CPC classification number: H01L21/00 ,  H01J37/3402 ,  H01L23/29 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A METHOD AND SYSTEM FOR RF SPUTTERING THIN CONDUCTING AND THIN INSULATING FILMA ON A SEMICONDUCTOR SUBSTRATE USING A FIRST ELECTRODE FOR SUPPORTING A SOURCE MATERIAL AND AN APERTURED SECOND ELECTRODE. THE RF VOLTAGE IS APPLIED ACROSS THE FIRST AND SECOND ELECTRODES. THE SUBSTRATE IS SUPPORTED BY A THIRD ELECTRODE AND EXPOSED TO ATOMS SPUTTERED FROM THE SOURCE WHICH PASS THROUGH THE APERTURED SECOND ELECTRODE. THE THIRD ELECTRODE MAY BE AT THE SAME POTENTIAL AS THE SECOND ELECTRODE, OR AT A DIFFERENT POTENTIAL TO CARRY OUT BIAS SPUTTERING. THE SYSTEM INCLUDES MULTIPLE PAIRS OF FIRST AND SECOND ELECTRODES FOR MULTIPLE FILM DEPOSITION WITHOUT BREADING VACUUM AND A ROTATING THIRD ELECTRODE WHICH MOVES THE SUBSTRATES PAST THE APERTURES IN THE SECOND ELECTRODES DURING SPUTTERING TO ELIMI-

    NATE SHADOWING AND TO FURTHER ENHANCE COOLING. A SHUTTER IS PROVIDED TO PREVENT CROSSCONTAMINATION OF THE IDLE SOURCES AND THE FILM BEING DEPOSITED ON THE SUBSTRATE.

    Ohmic contacts for semiconductors devices
    4.
    发明授权
    Ohmic contacts for semiconductors devices 失效
    用于半导体器件的OHMIC联系人

    公开(公告)号：US3667005A

    公开(公告)日：1972-05-30

    申请号：US3667005D

    申请日：1970-08-03

    Applicant: TEXAS INSTRUMENTS INC

    Inventor： CUNNINGHAM JAMES A ,  ORR COY D

    IPC: H01L21/00 ,  H01L23/485 ,  H01L23/522 ,  H01L27/00 ,  H01L1/14

    CPC classification number: H01L23/485 ,  H01L21/00 ,  H01L23/522 ,  H01L27/00 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Disclosed are methods for depositing multilayer ohmic contacts upon a substrate of semiconductor material disposed within a low pressure chamber; such including for example the particular features of upward sputtering of the various metal films, simultaneous sputtering of platinum with gold utilizing a sputtering cathode composed of platinum and gold, and adding hydrogen into an inert sputtering atmosphere to eliminate undesirable formation of oxides. This invention provides imporved adhesion of the sputtered metal films to the semiconductor surface and the silicon oxide, and provides the formation of the metal film which is substantially free of pin holes and which has substantially uniform resistivity.

    Abstract translation: 公开了一种在设置在低压室内的半导体材料的衬底上沉积多层欧姆接触的方法; 例如包括各种金属膜的向上溅射的特定特征，使用由铂和金构成的溅射阴极同时溅射铂，并将氢添加到惰性溅射气氛中以消除不期望的氧化物形成。 本发明提供了溅射金属膜对半导体表面和氧化硅的粘附，并提供了基本上没有针孔并且具有基本上均匀的电阻率的金属膜的形成。

    Insulated gate field effect transistor circuits and their method of fabrication
    5.
    发明授权
    Insulated gate field effect transistor circuits and their method of fabrication 失效
    绝缘栅场效应晶体管电路及其制造方法

    公开(公告)号：US3921282A

    公开(公告)日：1975-11-25

    申请号：US11542871

    申请日：1971-02-16

    Applicant: TEXAS INSTRUMENTS INC

    Inventor： CUNNINGHAM JAMES A ,  WAKEFIELD JR ROBERT H ,  GUIDRY JR MARK R

    IPC: H01L21/00 ,  H01L21/762 ,  H01L21/768 ,  H01L23/535 ,  B01J17/00

    CPC classification number: H01L23/535 ,  H01L21/00 ,  H01L21/762 ,  H01L21/76213 ,  H01L21/76838 ,  H01L2924/0002 ,  Y10S148/117 ,  Y10S148/122 ,  Y10S148/151 ,  Y10S438/981 ,  H01L2924/00

    Abstract: Insulated gate field effect transistor circuits utilizing transistors having a self-aligned gate, reduced parasitic capacitance and lower surface step-heights are fabricated with three levels of interconnects. The self-aligned gate transistors are fabricated with the use of a silicon nitride diffusion mask which also serves as an oxidation barrier in the formation of a thick oxide over the source and drain regions. Diffused interconnects are formed simultaneously with the source and drain region diffusions. The silicon nitride is then replaced with a more suitable dielectric, followed by the formation of polycrystalline silicon interconnects to provide source, drain and gate electrodes, and to provide a second level of interconnects which cross over the diffused interconnects at desired locations. An insulating layer is formed over the silicon interconnects and a metallization interconnect pattern, which crosses over the silicon interconnects at various desired locations is then formed to complete the circuit.

    Abstract translation: 采用具有自对准栅极，降低的寄生电容和较低表面阶跃高度的晶体管的绝缘栅场效应晶体管电路用三级互连制造。 使用氮化硅扩散掩模制造自对准栅极晶体管，氮化硅扩散掩模也用作在源极和漏极区域上形成厚氧化物的氧化屏障。 扩散互连与源区和漏区扩散同时形成。 然后用更合适的电介质代替氮化硅，随后形成多晶硅互连以提供源极，漏极和栅电极，并提供在期望位置上跨越扩散互连的第二级互连。 在硅互连上形成绝缘层，然后形成在各种所需位置上穿过硅互连的金属化互连图案以完成电路。

    Metallization system for semiconductors
    10.
    发明授权
    Metallization system for semiconductors 失效
    用于半导体的金属化系统

    公开(公告)号：US3654526A

    公开(公告)日：1972-04-04

    申请号：US3654526D

    申请日：1970-05-19

    Applicant: TEXAS INSTRUMENTS INC

    Inventor： CUNNINGHAM JAMES A ,  FULLER CLYDE R ,  HOOPER ROBERT C ,  WAKEFIELD ROBERT H

    IPC: H01L21/00 ,  H01L23/482 ,  H01L23/522 ,  H01L23/532 ,  H01L5/02

    CPC classification number: H01L23/53295 ,  H01L21/00 ,  H01L23/4822 ,  H01L23/522 ,  H01L23/5329 ,  H01L24/01 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/1306 ,  H01L2924/14 ,  H01L2924/00

    Abstract: A metallization system for semiconductor devices includes a first layer of aluminum a part of which is in ohmic contact with a silicon substrate and devices thereon, the other part of which overlies an insulating layer. A second layer of molybdenum is deposited on the aluminum layer. The aluminum and molybdenum are photoetched into a predetermined pattern which ohmically contacts the silicon and overlies an insulating layer, usually of silicon dioxide. Thereafter a variety of techniques and lead systems can be used. For example, a second layer of insulating material can be applied over the first level aluminum-molybdenum metallization system and the first layer of insulating material. The second level of insulating material can then be selectively etched to expose predetermined portions of the first level lead system. Thereafter, beam leads can be attached to the first level metallization system; or bonding pads can be formed in ohmic contact with the first level metallization system. Alternatively, a second level metallization system can be utilized where it becomes necessary to conductively connect various components on the semiconductor device by lead cross-overs. A third layer of insulating material can then be applied on top of the second level metallization system. After selective etching of the second level insulating material, beam leads, bonding pads or even a third level metallization system can be applied.

    Abstract translation: 用于半导体器件的金属化系统包括第一层铝，其一部分与硅衬底和其上的器件欧姆接触，其另一部分覆盖绝缘层。 第二层钼沉积在铝层上。 铝和钼被光刻成预定的图案，其与硅接触并覆盖绝缘层，通常为二氧化硅。 此后可以使用各种技术和引导系统。 例如，可以在第一级铝 - 钼金属化系统和第一绝缘材料层上施加第二层绝缘材料。 然后可以选择性地蚀刻第二级绝缘材料以暴露第一级引线系统的预定部分。 此后，光束引线可以附接到第一级金属化系统; 或者接合焊盘可以与第一级金属化系统欧姆接触形成。 或者，可以利用第二级金属化系统，其中需要通过引线交叉导电地连接半导体器件上的各种部件。 然后可以将第三层绝缘材料施加在第二层金属化系统的顶部上。 在选择性地蚀刻第二级绝缘材料之后，可以应用光束引线，焊盘或甚至第三级金属化系统。

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