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公开(公告)号:US20210105021A1
公开(公告)日:2021-04-08
申请号:US17061730
申请日:2020-10-02
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor: Jawaharlal TANGUDU , Pankaj GUPTA , Sreenath Narayanan POTTY , Ajai PAULOSE , Chandrasekhar SRIRAM , Mahesh Ravi VARMA , Shabbar Abbasi VEJLANI , Neeraj SHRIVASTAVA , Himanshu VARSHNEY , Divyeshkumar Mahendrabhai PATEL , Raju Kharataram CHAUDHARI
Abstract: A non-linearity correction circuit includes a non-linearity coefficient estimation circuit. The non-linearity coefficient estimation circuit includes a data capture circuit, a non-linearity term generation circuit, a time-to-frequency conversion circuit, a bin identification circuit, a residual non-linearity conversion circuit, and a non-linearity coefficient generation circuit. The non-linearity term generation circuit is coupled to the data capture circuit. The time-to-frequency conversion circuit is coupled to the data capture circuit and the non-linearity term generation circuit. The bin identification circuit is coupled to the time-to-frequency conversion circuit. The residual non-linearity conversion circuit is coupled to the bin identification circuit. The non-linearity coefficient generation circuit is coupled to the bin identification circuit and the residual non-linearity conversion circuit.
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公开(公告)号:US20240250690A1
公开(公告)日:2024-07-25
申请号:US18326527
申请日:2023-05-31
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor: Ajai PAULOSE , Avarind GANESAN
CPC classification number: H03M1/1023 , H03M1/089
Abstract: A system includes: a first device; and a second device coupled to the first device. The second device has a receiver. The receiver has a comparator and a controller. The comparator has an adjustment terminal. The controller has an input and an output. The output of the controller is coupled to the adjustment terminal of the comparator. The controller is configured to: obtain an offset estimation model; receive an input voltage at its input; determine a comparator offset responsive to the offset estimation model and the input voltage; and provide an adjustment control signal to its output responsive to the determined comparator offset.
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公开(公告)号:US20200327950A1
公开(公告)日:2020-10-15
申请号:US16916911
申请日:2020-06-30
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor: Aravind GANESAN , Jaiganesh BALAKRISHNAN , Nagarajan VISWANATHAN , Yeswanth GUNTUPALLI , Ajai PAULOSE , Mathews JOHN , Jagannathan VENKATARAMAN , Neeraj SHRIVASTAVA
Abstract: A one-time write, read-only memory for storing trimming parameters includes an address pointer table, a fixed packet portion, and a flexible packet portion. The fixed packet portion includes one or more fixed packets, each fixed packet including trimming parameters for a component identified for trimming during a design phase. The flexible packet portion includes one or more flexible packets of different types. Each flexible packet includes trimming parameters for a component identified for trimming after the design phase. One packet type includes a length section and a number of fields equal to a value stored in the length section. Each field includes an address, a trimming parameter, and a mask. Another packet type includes trimming parameters associated with operands in operating instructions for a microcontroller, where the operands include an address and a mask.
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公开(公告)号:US20200152284A1
公开(公告)日:2020-05-14
申请号:US16235698
申请日:2018-12-28
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor: Aravind GANESAN , Jaiganesh BALAKRISHNAN , Nagarajan VISWANATHAN , Yeswanth GUNTUPALLI , Ajai PAULOSE , Mathews JOHN , Jagannathan VENKATARAMAN , Neeraj SHRIVASTAVA
Abstract: A one-time write, read-only memory for storing trimming parameters includes an address pointer table, a fixed packet portion, and a flexible packet portion. The fixed packet portion includes one or more fixed packets, each fixed packet including trimming parameters for a component identified for trimming during a design phase. The flexible packet portion includes one or more flexible packets of different types. Each flexible packet includes trimming parameters for a component identified for trimming after the design phase. One packet type includes a length section and a number of fields equal to a value stored in the length section. Each field includes an address, a trimming parameter, and a mask. Another packet type includes trimming parameters associated with operands in operating instructions for a microcontroller, where the operands include an address and a mask.
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