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公开(公告)号:US20230275442A1
公开(公告)日:2023-08-31
申请号:US18313658
申请日:2023-05-08
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor: Mustapha EL MARKHI , Alejandro VERA , Tonmoy ROY , Rohit BHAN
IPC: H02J7/00
CPC classification number: H02J7/0031 , H02J7/00 , H02J7/00302 , H02J7/00304
Abstract: Aspects of the disclosure provide for a circuit. In at least some examples, the circuit includes a logic circuit, a first comparator, a second comparator, and an AND logic circuit. The logic circuit has an output and the first comparator has a first input coupled to an input voltage (VIN) pin, a second input configured to receive a Vin under voltage lockout (VINUVLO) threshold value, and an output. The second comparator has a first input coupled to a power middle (PMID) pin, a second input coupled to a battery pin, and an output and the AND logic circuit has a first input coupled to the output of the logic circuit, a second input coupled to the output of the first comparator, a third input coupled to the output of the second comparator, and an output coupled to an input of a field-effect transistor (FET) control circuit.
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公开(公告)号:US20170317625A1
公开(公告)日:2017-11-02
申请号:US15142219
申请日:2016-04-29
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor: Alejandro VERA , Shyamsunder BALASUBRAMANIAN , Toshio YAMANAKA , Toru TANAKA
Abstract: A voltage regulator includes an output transistor, an error amplifier coupled to the output transistor, a cascode transistor coupled to the output transistor in series, and a cascode bias circuit coupled to the cascode transistor and the output transistor. The output transistor is configured to generate an output signal at a first voltage. The error amplifier is configured to receive a reference signal. The cascode bias circuit is configured to bias the cascode transistor such that, in response to a drain-to-source short circuit of the output transistor, the cascode transistor generates the output signal at the first voltage.
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