公开(公告)号：US20190199332A1

公开(公告)日：2019-06-27

申请号：US15854741

申请日：2017-12-26

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Basavaraj G. GORGUDDI ,  Ani XAVIER

IPC: H03K5/1252 ,  H01L27/02 ,  H01L27/06 ,  H01L23/535 ,  H01L23/528

CPC classification number: H03K5/1252 ,  H01L23/528 ,  H01L23/535 ,  H01L27/0207 ,  H01L27/0629 ,  H03M1/124

Abstract: In some examples, an apparatus includes a plurality of first transistors coupled to a first input terminal and a first output terminal. The apparatus also includes a plurality of second transistors coupled to a second input terminal and a second output terminal. The apparatus further includes a plurality of first dummy transistors coupled to the first input terminal and the second output terminal. The apparatus also includes a plurality of second dummy transistors coupled to the second input terminal and the first output terminal.

公开(公告)号：US20190207617A1

公开(公告)日：2019-07-04

申请号：US16104978

申请日：2018-08-20

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Ani XAVIER ,  Neeraj SHRIVASTAVA ,  Arun MOHAN

IPC: H03M1/12 ,  G06F1/04

CPC classification number: H03M1/1245 ,  G06F1/04 ,  G11C27/02

Abstract: In some examples, a system includes a first transistor comprising a first source terminal coupled to a first input terminal, a first drain terminal coupled to a first top plate sampling capacitor, and a first gate terminal. The system also includes a first input-dependent dual clock boost circuit coupled to the first input terminal via a first boost circuit input and to the first gate terminal via a first boost circuit output. The system further includes a second transistor comprising a second source terminal coupled to a second input terminal, a second drain terminal coupled to a second top plate sampling capacitor, and a second gate terminal. The system also includes a second input-dependent dual clock boost circuit coupled to the second input terminal via a second boost circuit input and to the second gate terminal of the second transistor via a second boost circuit output.

公开(公告)号：US20220197330A1

公开(公告)日：2022-06-23

申请号：US17245711

申请日：2021-04-30

Applicant: Texas Instruments Incorporated

Inventor： Ani XAVIER ,  Jagannathan VENKATARAMAN ,  Raviteja VELISETTI

IPC: G06F1/10 ,  H03L7/081

Abstract: A first logic gate has a first input coupled to a first circuit input or a second circuit input, a second input selectively coupled to a third circuit input or a fourth circuit input, and a first output. The first output has a signal with a duty cycle that is a function of a phase difference between a first signal on the first input and a second signal on the second input. A second logic gate has a third input coupled to the third circuit input or the fourth circuit input, a fourth input coupled to the second circuit input or the fourth circuit input, and a second output. The second output has a signal with a duty cycle that is a function of a phase difference between a third signal on the third input and a fourth signal on the fourth input.