公开(公告)号：US20190207617A1

公开(公告)日：2019-07-04

申请号：US16104978

申请日：2018-08-20

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Ani XAVIER ,  Neeraj SHRIVASTAVA ,  Arun MOHAN

IPC: H03M1/12 ,  G06F1/04

CPC classification number: H03M1/1245 ,  G06F1/04 ,  G11C27/02

Abstract: In some examples, a system includes a first transistor comprising a first source terminal coupled to a first input terminal, a first drain terminal coupled to a first top plate sampling capacitor, and a first gate terminal. The system also includes a first input-dependent dual clock boost circuit coupled to the first input terminal via a first boost circuit input and to the first gate terminal via a first boost circuit output. The system further includes a second transistor comprising a second source terminal coupled to a second input terminal, a second drain terminal coupled to a second top plate sampling capacitor, and a second gate terminal. The system also includes a second input-dependent dual clock boost circuit coupled to the second input terminal via a second boost circuit input and to the second gate terminal of the second transistor via a second boost circuit output.

公开(公告)号：US20200212921A1

公开(公告)日：2020-07-02

申请号：US16234685

申请日：2018-12-28

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sai Aditya KrishnaSwamy NURANI ,  Arun MOHAN ,  Shagun DUSAD ,  Neeraj SHRIVASTAVA

IPC: H03M1/06 ,  H03F1/32 ,  H03F3/45

Abstract: A top-plate sampling analog-to-digital converter (ADC) circuit includes a first ADC stage and a residue amplifier coupled to the first ADC stage. The residue amplifier comprises a first transistor with a control terminal, a first current terminal, and a second current terminal. The residue amplifier also comprises a second transistor with a control terminal, a first current terminal, and a second current terminal. The residue amplifier also comprises a linearity adjustment circuit coupled to a second current terminal of at least one of the first transistor and the second transistor. The linearity adjustment circuit comprises at least one switch that changes its state as a function of an input sampling phase and a gain phase of the residue amplifier.

公开(公告)号：US20190207564A1

公开(公告)日：2019-07-04

申请号：US15859431

申请日：2017-12-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Ani Xavier ,  Neeraj SHRIVASTAVA ,  Arun MOHAN ,  Shagun DUSAD

IPC: H03F1/30 ,  H03F1/02 ,  H03F3/45

CPC classification number: H03F1/301 ,  H03F1/0205 ,  H03F3/45179 ,  H03F2203/45286

Abstract: In some examples, an amplifier stage includes a voltage-gain amplifier stage and a negative capacitance circuit coupled to the voltage-gain amplifier stage, the negative capacitance circuit comprising a first transistor that provides a first temperature-biased current.

公开(公告)号：US20190296758A1

公开(公告)日：2019-09-26

申请号：US16358456

申请日：2019-03-19

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Arun MOHAN ,  Neeraj SHRIVASTAVA

IPC: H03M1/12 ,  H03M1/38 ,  H03M1/06 ,  H03F3/04

Abstract: An analog-to-digital converter including a first stage and a second stage. The first stage includes a first sample-and-hold (SH) having an input coupled to a voltage input node of the ADC, and having a first SH output. The first stage also includes a buffer, a first flash converter and a first digital-to-analog converter (DAC). The buffer has an input coupled to the first SH output and has a buffer output. The first flash converter has an input coupled to the first SH output, and has a first flash converter output. The first DAC has an input coupled to the first flash converter output. The second stage includes a second flash converter having an input coupled to the buffer output.

公开(公告)号：US20160315630A1

公开(公告)日：2016-10-27

申请号：US15136368

申请日：2016-04-22

Applicant: Texas Instruments Incorporated

Inventor： Gehesh EDAKKUTTATHIL MUHAMMED ,  Naveen KV ,  Arun MOHAN ,  Shagun DUSAD

IPC: H03M1/12

CPC classification number: H03M1/12 ,  H01G4/30 ,  H01G4/38 ,  H01G4/385 ,  H01L23/5223 ,  H01L27/0805 ,  H01L28/90 ,  H03M1/804

Abstract: The disclosure provides a capacitor array. The capacitor array includes one or more first metal plates vertically stacked parallel to each other. A second metal plate is horizontally stacked to couple one end of each first metal plate of the one or more first metal plates. One or more third metal plates are vertically stacked parallel to the one or more first metal plates. Each third metal plate of the one or more third metal plates is stacked between two first metal plates.

Abstract translation: 本公开提供了一种电容器阵列。 电容器阵列包括彼此垂直堆叠的一个或多个第一金属板。 水平堆叠的第二金属板将一个或多个第一金属板的每个第一金属板的一端连接。 一个或多个第三金属板垂直堆叠成平行于一个或多个第一金属板。 一个或多个第三金属板的每个第三金属板堆叠在两个第一金属板之间。