High performance super-beta NPN (SBNPN)

    公开(公告)号:US11205718B1

    公开(公告)日:2021-12-21

    申请号:US16695718

    申请日:2019-11-26

    Abstract: An integrated circuit includes one or more bipolar transistors, each including a first dielectric layer located over a semiconductor layer having a first conductivity type, the dielectric layer including an opening. A second dielectric layer is located between the first dielectric layer and the semiconductor layer. The second dielectric layer defines a first recess between the first dielectric layer and the semiconductor substrate at a first side of the opening, and a second recess between the first dielectric layer and the semiconductor substrate at a second opposite side of the opening. A first doped region of the semiconductor layer is located under the opening, the first doped region having a different second conductivity type and a first width. A second doped region of the semiconductor layer is also under the opening, the second doped region having the second conductivity type and underlying the first recess and the second recess.

    High performance super-beta NPN (SBNPN)

    公开(公告)号:US10032868B2

    公开(公告)日:2018-07-24

    申请号:US15261024

    申请日:2016-09-09

    Abstract: A method for making a super β NPN (SBNPN) transistor includes depositing a tetraethyl orthosilicate (TEOS) layer on a P type epitaxial layer; depositing a nitride layer on the TEOS layer; patterning an emitter region of the SBNPN transistor by selectively etching away portions of the nitride layer and the TEOS layer; depositing a second TEOS layer on top of the nitride layer, along sides of the nitride layer and the TEOS layer, and on top of the P type epitaxial layer; and implanting the P type epitaxial layer through the second TEOS layer with N type ions to form the emitter region of the SBNPN transistor.

Patent Agency Ranking