公开(公告)号：US08754484B2

公开(公告)日：2014-06-17

申请号：US13967918

申请日：2013-08-15

Applicant: Texas Instruments Incorporated

Inventor： Hiroshi Yasuda ,  Berthold Staufer

IPC: H01L27/06 ,  H01L29/732 ,  H01L29/78

CPC classification number: H01L27/0623 ,  H01L21/8249 ,  H01L29/1004 ,  H01L29/66287 ,  H01L29/732 ,  H01L29/7833

Abstract: A process of forming an integrated circuit containing a bipolar transistor and an MOS transistor, by forming a base layer of the bipolar transistor using a non-selective epitaxial process so that the base layer has a single crystalline region on a collector active area and a polycrystalline region on adjacent field oxide, and concurrently implanting the MOS gate layer and the polycrystalline region of the base layer, so that the base-collector junction extends into the substrate less than one-third of the depth of the field oxide, and vertically cumulative doping density of the polycrystalline region of the base layer is between 80 percent and 125 percent of a vertically cumulative doping density of the MOS gate. An integrated circuit containing a bipolar transistor and an MOS transistor formed by the described process.

Abstract translation: 通过使用非选择性外延工艺形成双极型晶体管的基极层，使得基极层在集电极有源区域上具有单一结晶区域和多晶硅层，形成包含双极晶体管和MOS晶体管的集成电路的工艺 区域，并且同时注入基极层的MOS栅极层和多晶区域，使得基极 - 集电极结延伸到小于场氧化物深度的三分之一的衬底中，并且垂直累积掺杂 基极层的多晶区域的密度在MOS栅极的垂直累积掺杂密度的80％至125％之间。 包含双极晶体管和通过所描述的工艺形成的MOS晶体管的集成电路。

公开(公告)号：US11205718B1

公开(公告)日：2021-12-21

申请号：US16695718

申请日：2019-11-26

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Bernhard Benna ,  Berthold Staufer

IPC: H01L29/737 ,  H01L29/66 ,  H01L21/265 ,  H01L21/285 ,  H01L29/45 ,  H01L29/167 ,  H01L29/08 ,  H01L29/10 ,  H01L29/165

Abstract: An integrated circuit includes one or more bipolar transistors, each including a first dielectric layer located over a semiconductor layer having a first conductivity type, the dielectric layer including an opening. A second dielectric layer is located between the first dielectric layer and the semiconductor layer. The second dielectric layer defines a first recess between the first dielectric layer and the semiconductor substrate at a first side of the opening, and a second recess between the first dielectric layer and the semiconductor substrate at a second opposite side of the opening. A first doped region of the semiconductor layer is located under the opening, the first doped region having a different second conductivity type and a first width. A second doped region of the semiconductor layer is also under the opening, the second doped region having the second conductivity type and underlying the first recess and the second recess.