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    Embedded universal serial bus 2 repeater
    5.
    发明授权
    Embedded universal serial bus 2 repeater 有权

    公开(公告)号：US10762016B2

    公开(公告)日：2020-09-01

    申请号：US16404494

    申请日：2019-05-06

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Win Naing Maung ,  Douglas Edward Wente ,  Mustafa Ulvi Erdogan ,  Huanzhang Huang ,  Saurabh Goyal ,  Bhupendra Sharma

    IPC: G06F13/38 ,  G06F13/42 ,  H04B3/36

    Abstract: Aspects of the disclosure provide for a circuit including a squelch detector having a first input coupled to a first node and configured to receive a positive component of a differential signal with a floating center tap, a second input coupled to a second node and configured to receive a negative component of the differential signal, and an output coupled to a logic circuit, a first resistor coupled between the first node and a third node, a second resistor coupled between the third node and the second node, a third resistor coupled between the first node and a fourth node, a fourth resistor coupled between the fourth node and the second node, a capacitor coupled between the fourth node and a ground terminal, a comparator having a first input coupled to the third node, a second input coupled to a fifth node, and an output coupled to the logic circuit.

    Delta sigma modulator apparatus and method to mitigate DAC error induced offset and even order harmonic distortion
    6.
    发明授权
    Delta sigma modulator apparatus and method to mitigate DAC error induced offset and even order harmonic distortion 有权
    ΔΣ调制器装置和方法来减轻DAC误差感应偏移和偶次谐波失真

    公开(公告)号：US09413383B1

    公开(公告)日：2016-08-09

    申请号：US14816272

    申请日：2015-08-03

    Applicant: Texas Instruments Incorporated

    Inventor： Bhupendra Sharma

    IPC: H03M3/00 ,  H03M1/00

    CPC classification number: H03M3/384 ,  H03M3/34 ,  H03M3/454

    Abstract: Delta sigma modulators, apparatus and methods mitigate DAC error induced offset and even order harmonic distortion in a delta sigma modulator by chopping a digital output stream of a forward circuit path using a digital modulator or digital chopper circuit in a feedback circuit to create a DAC digital input signal responsive to a chopper clock signal having a clock rate lower than a DSM quantizer clock signal, and chopping a differential DAC output signal using an analog chopper circuit responsive to the chopper clock signal to provide a differential feedback signal to a forward circuit path of the DSM to mitigate DAC error induced offset and even order harmonic distortion in the digital output stream.

    Abstract translation: ΔΣ调制器，装置和方法通过在反馈电路中使用数字调制器或数字斩波电路斩波正向电路路径的数字输出流来减轻ΔΣ调制器中的DAC误差感应偏移和偶次谐波失真，以产生DAC数字 响应于具有低于DSM量化器时钟信号的时钟速率的斩波时钟信号的输入信号，并且使用响应于斩波时钟信号的模拟斩波电路斩波差分DAC输出信号，以将差分反馈信号提供给 DSM减轻数字输出流中的DAC误差感应偏移和偶次次谐波失真。

    Embedded universal serial bus 2 repeater
    8.
    发明授权
    Embedded universal serial bus 2 repeater 有权

    公开(公告)号：US10922255B2

    公开(公告)日：2021-02-16

    申请号：US16939725

    申请日：2020-07-27

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Win Naing Maung ,  Douglas Edward Wente ,  Mustafa Ulvi Erdogan ,  Huanzhang Huang ,  Saurabh Goyal ,  Bhupendra Sharma

    IPC: G06F13/42 ,  G06F13/38 ,  H04B3/36

    Abstract: Aspects of the disclosure provide for a circuit including a squelch detector having a first input coupled to a first node and configured to receive a positive component of a differential signal with a floating center tap, a second input coupled to a second node and configured to receive a negative component of the differential signal, and an output coupled to a logic circuit, a first resistor coupled between the first node and a third node, a second resistor coupled between the third node and the second node, a third resistor coupled between the first node and a fourth node, a fourth resistor coupled between the fourth node and the second node, a capacitor coupled between the fourth node and a ground terminal, a comparator having a first input coupled to the third node, a second input coupled to a fifth node, and an output coupled to the logic circuit.

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