公开(公告)号：US11515870B2

公开(公告)日：2022-11-29

申请号：US17234170

申请日：2021-04-19

Applicant: Texas Instruments Incorporated

Inventor： Roland Karl Son ,  Craig Bennett Greenberg ,  Indumini Ramuthu

IPC: H03K17/08 ,  H03K17/14 ,  H03K17/687

Abstract: A system includes an output terminal and a linear switch circuit coupled to the output terminal. The linear switch circuit includes a first power field-effect transistor (FET) having: a first channel width; a control terminal; a first current terminal; and a second current terminal, wherein the second current terminal is coupled to the output terminal. The linear switch circuit also includes a second power FET having: a second channel width smaller than the first channel width; a control terminal; a first current terminal coupled to the first current terminal of the first power FET; and a second current terminal coupled to the output terminal. The system also comprises a control circuit coupled to the control terminal of the first power FET and to the control terminal of the second power FET. The control circuit detects a drain-to-source voltage (VDS) saturation condition and controls the first and second power FETs accordingly.

公开(公告)号：US20210242866A1

公开(公告)日：2021-08-05

申请号：US17234170

申请日：2021-04-19

Applicant: Texas Instruments Incorporated

Inventor： Roland Karl Son ,  Craig Bennett Greenberg ,  Indumini Ramuthu

IPC: H03K17/14 ,  H03K17/687

Abstract: A system includes an output terminal and a linear switch circuit coupled to the output terminal. The linear switch circuit includes a first power field-effect transistor (FET) having: a first channel width; a control terminal; a first current terminal; and a second current terminal, wherein the second current terminal is coupled to the output terminal. The linear switch circuit also includes a second power FET having: a second channel width smaller than the first channel width; a control terminal; a first current terminal coupled to the first current terminal of the first power FET; and a second current terminal coupled to the output terminal. The system also comprises a control circuit coupled to the control terminal of the first power FET and to the control terminal of the second power FET. The control circuit detects a drain-to-source voltage (VDS) saturation condition and controls the first and second power FETs accordingly.

公开(公告)号：US11018663B2

公开(公告)日：2021-05-25

申请号：US16984015

申请日：2020-08-03

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Roland Karl Son ,  Craig Bennett Greenberg ,  Indumini Ranmuthu

IPC: H03K17/08 ,  H03K17/14 ,  H03K17/687

Abstract: A system includes an output terminal and a linear switch circuit coupled to the output terminal. The linear switch circuit includes a first power field-effect transistor (FET) having: a first channel width; a control terminal; a first current terminal; and a second current terminal, wherein the second current terminal is coupled to the output terminal. The linear switch circuit also includes a second power FET having: a second channel width smaller than the first channel width; a control terminal; a first current terminal coupled to the first current terminal of the first power FET; and a second current terminal coupled to the output terminal. The system also comprises a control circuit coupled to the control terminal of the first power FET and to the control terminal of the second power FET. The control circuit detects a drain-to-source voltage (VDS) saturation condition and controls the first and second power FETs accordingly.