公开(公告)号：US20170063369A1

公开(公告)日：2017-03-02

申请号：US15244814

申请日：2016-08-23

Applicant: Texas Instruments Incorporated

Inventor： Emmanuel Osei Boakye ,  Roland Karl Son ,  Juergen Luebbe

IPC: H03K17/687 ,  H03K3/0233 ,  H02M3/07

CPC classification number: H03K3/02337 ,  H02M1/08 ,  H03K17/0822

Abstract: In described examples, a transistor has: a source and a drain coupled between a supply voltage and an output terminal; and a gate terminal. A charge pump has: an output node coupled to the gate terminal; and a clock input. An oscillator is coupled to generate a clock signal. A clock enable circuit is coupled to: receive the clock signal; and selectively output the clock signal to the clock input, responsive to an enable signal. A comparator is coupled to output the enable signal in response to a comparison between a reference current and a current through a series resistor. The series resistor is coupled to the gate terminal.

Abstract translation: 在所述示例中，晶体管具有：耦合在电源电压和输出端之间的源极和漏极; 和门终端。 电荷泵具有：耦合到栅极端子的输出节点; 和时钟输入。 振荡器被耦合以产生时钟信号。 时钟使能电路耦合到：接收时钟信号; 并且响应于使能信号而选择性地将时钟信号输出到时钟输入端。 耦合比较器以响应于参考电流和通过串联电阻器的电流之间的比较来输出使能信号。 串联电阻耦合到栅极端子。

公开(公告)号：US20210242866A1

公开(公告)日：2021-08-05

申请号：US17234170

申请日：2021-04-19

Applicant: Texas Instruments Incorporated

Inventor： Roland Karl Son ,  Craig Bennett Greenberg ,  Indumini Ramuthu

IPC: H03K17/14 ,  H03K17/687

Abstract: A system includes an output terminal and a linear switch circuit coupled to the output terminal. The linear switch circuit includes a first power field-effect transistor (FET) having: a first channel width; a control terminal; a first current terminal; and a second current terminal, wherein the second current terminal is coupled to the output terminal. The linear switch circuit also includes a second power FET having: a second channel width smaller than the first channel width; a control terminal; a first current terminal coupled to the first current terminal of the first power FET; and a second current terminal coupled to the output terminal. The system also comprises a control circuit coupled to the control terminal of the first power FET and to the control terminal of the second power FET. The control circuit detects a drain-to-source voltage (VDS) saturation condition and controls the first and second power FETs accordingly.

公开(公告)号：US11515870B2

公开(公告)日：2022-11-29

申请号：US17234170

申请日：2021-04-19

Applicant: Texas Instruments Incorporated

Inventor： Roland Karl Son ,  Craig Bennett Greenberg ,  Indumini Ramuthu

IPC: H03K17/08 ,  H03K17/14 ,  H03K17/687

Abstract: A system includes an output terminal and a linear switch circuit coupled to the output terminal. The linear switch circuit includes a first power field-effect transistor (FET) having: a first channel width; a control terminal; a first current terminal; and a second current terminal, wherein the second current terminal is coupled to the output terminal. The linear switch circuit also includes a second power FET having: a second channel width smaller than the first channel width; a control terminal; a first current terminal coupled to the first current terminal of the first power FET; and a second current terminal coupled to the output terminal. The system also comprises a control circuit coupled to the control terminal of the first power FET and to the control terminal of the second power FET. The control circuit detects a drain-to-source voltage (VDS) saturation condition and controls the first and second power FETs accordingly.

公开(公告)号：US09831852B2

公开(公告)日：2017-11-28

申请号：US15244814

申请日：2016-08-23

Applicant: Texas Instruments Incorporated

Inventor： Emmanuel Osei Boakye ,  Roland Karl Son ,  Juergen Luebbe

IPC: H03K17/687 ,  H03K3/0233 ,  H02M1/08 ,  H03K17/082

CPC classification number: H03K3/02337 ,  H02M1/08 ,  H03K17/0822

Abstract: In described examples, a transistor has: a source and a drain coupled between a supply voltage and an output terminal; and a gate terminal. A charge pump has: an output node coupled to the gate terminal; and a clock input. An oscillator is coupled to generate a clock signal. A clock enable circuit is coupled to: receive the clock signal; and selectively output the clock signal to the clock input, responsive to an enable signal. A comparator is coupled to output the enable signal in response to a comparison between a reference current and a current through a series resistor. The series resistor is coupled to the gate terminal.

公开(公告)号：US20170047731A1

公开(公告)日：2017-02-16

申请号：US15232521

申请日：2016-08-09

Applicant: Texas Instruments Incorporated

Inventor： Sujan Kundapur Manohar ,  Roland Karl Son ,  Juergen Luebbe ,  Eddie W. Yu

IPC: H02H9/02 ,  H03K5/08 ,  H03K17/687

CPC classification number: H03K5/08 ,  H02H3/08 ,  H02H3/087 ,  H02H3/18 ,  H02H9/02 ,  H03K17/08122 ,  H03K17/0822

Abstract: In described examples, a power interface subsystem includes power transistors, each having: a conduction path coupled between a battery terminal and an accessory terminal; and a control terminal. A differential amplifier has: a first input coupled to the battery terminal; a second input coupled to the accessory terminal; and an output node. An offset voltage source is coupled to cause an offset of a selected polarity at one of the inputs to the differential amplifier. The offset has a first polarity in a first operating mode and a second polarity in a second operating mode. Gate control circuitry is coupled to apply a control level at the control terminal(s) of selected one(s) of the power transistors responsive to a voltage at the output node, and to apply an off-state control level to the control terminal(s) of unselected one(s) of the power transistors.

Abstract translation: 在所述示例中，电源接口子系统包括功率晶体管，每个功率晶体管具有：耦合在电池端子和附件端子之间的导电路径; 和控制终端。 差分放大器具有：耦合到电池端子的第一输入; 耦合到附件终端的第二输入; 和输出节点。 偏移电压源被耦合以在所述差分放大器的输入之一处引起所选极性的偏移。 偏移在第一操作模式中具有第一极性，在第二操作模式中具有第二极性。 门控制电路被耦合以响应于输出节点处的电压而在功率晶体管的所选择的一个或多个控制端上施加控制电平，并且向控制端施加截止状态控制电平（ s）的未选择的一个或多个功率晶体管。

公开(公告)号：US11018663B2

公开(公告)日：2021-05-25

申请号：US16984015

申请日：2020-08-03

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Roland Karl Son ,  Craig Bennett Greenberg ,  Indumini Ranmuthu

IPC: H03K17/08 ,  H03K17/14 ,  H03K17/687

Abstract: A system includes an output terminal and a linear switch circuit coupled to the output terminal. The linear switch circuit includes a first power field-effect transistor (FET) having: a first channel width; a control terminal; a first current terminal; and a second current terminal, wherein the second current terminal is coupled to the output terminal. The linear switch circuit also includes a second power FET having: a second channel width smaller than the first channel width; a control terminal; a first current terminal coupled to the first current terminal of the first power FET; and a second current terminal coupled to the output terminal. The system also comprises a control circuit coupled to the control terminal of the first power FET and to the control terminal of the second power FET. The control circuit detects a drain-to-source voltage (VDS) saturation condition and controls the first and second power FETs accordingly.

公开(公告)号：US10979037B2

公开(公告)日：2021-04-13

申请号：US16167151

申请日：2018-10-22

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sujan Kundapur Manohar ,  Roland Karl Son ,  Juergen Luebbe ,  Eddie W. Yu

IPC: H02H3/087 ,  H03K5/08 ,  H03K17/0812 ,  H02H3/18 ,  H02H3/08 ,  H03K17/082 ,  H02H9/02 ,  H02H3/44

Abstract: In described examples, a power interface subsystem includes power transistors, each having: a conduction path coupled between a battery terminal and an accessory terminal; and a control terminal. A differential amplifier has: a first input coupled to the battery terminal; a second input coupled to the accessory terminal; and an output node. An offset voltage source is coupled to cause an offset of a selected polarity at one of the inputs to the differential amplifier. The offset has a first polarity in a first operating mode and a second polarity in a second operating mode. Gate control circuitry is coupled to apply a control level at the control terminal(s) of selected one(s) of the power transistors responsive to a voltage at the output node, and to apply an off-state control level to the control terminal(s) of unselected one(s) of the power transistors.

公开(公告)号：US20190058463A1

公开(公告)日：2019-02-21

申请号：US16167151

申请日：2018-10-22

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sujan Kundapur Manohar ,  Roland Karl Son ,  Juergen Luebbe ,  Eddie W. Yu

IPC: H03K5/08 ,  H03K17/0812 ,  H02H3/18 ,  H02H3/087 ,  H02H3/08 ,  H03K17/082 ,  H02H9/02

Abstract: In described examples, a power interface subsystem includes power transistors, each having: a conduction path coupled between a battery terminal and an accessory terminal; and a control terminal. A differential amplifier has: a first input coupled to the battery terminal; a second input coupled to the accessory terminal; and an output node. An offset voltage source is coupled to cause an offset of a selected polarity at one of the inputs to the differential amplifier. The offset has a first polarity in a first operating mode and a second polarity in a second operating mode. Gate control circuitry is coupled to apply a control level at the control terminal(s) of selected one(s) of the power transistors responsive to a voltage at the output node, and to apply an off-state control level to the control terminal(s) of unselected one(s) of the power transistors.

公开(公告)号：US10116291B2

公开(公告)日：2018-10-30

申请号：US15232521

申请日：2016-08-09

Applicant: Texas Instruments Incorporated

Inventor： Sujan Kundapur Manohar ,  Roland Karl Son ,  Juergen Luebbe ,  Eddie W. Yu

IPC: H02H3/00 ,  H03K5/08 ,  H03K17/0812 ,  H02H3/18 ,  H02H3/08 ,  H03K17/082 ,  H02H9/02 ,  H02H3/087

Abstract: In described examples, a power interface subsystem includes power transistors, each having: a conduction path coupled between a battery terminal and an accessory terminal; and a control terminal. A differential amplifier has: a first input coupled to the battery terminal; a second input coupled to the accessory terminal; and an output node. An offset voltage source is coupled to cause an offset of a selected polarity at one of the inputs to the differential amplifier. The offset has a first polarity in a first operating mode and a second polarity in a second operating mode. Gate control circuitry is coupled to apply a control level at the control terminal(s) of selected one(s) of the power transistors responsive to a voltage at the output node, and to apply an off-state control level to the control terminal(s) of unselected one(s) of the power transistors.