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公开(公告)号：US20240272670A1
公开(公告)日：2024-08-15
申请号：US18645579
申请日：2024-04-25
Applicant: Texas Instruments Incorporated
Inventor： Michael Ryan Hanschke , Pankaj Pandey , Joseph Pham , David Wayne Evans
CPC classification number: G06F1/14 , G06F11/1604 , H04L7/0037 , H04L7/0045
Abstract: A clock data recovery circuit includes a deglitch filter circuit and a timer circuit. The deglitch filter circuit is configured to remove pulses of less than a particular duration from a data signal to produce a deglitched data signal. The timer circuit is coupled to the deglitch filter, and is configured to compare a duration of a pulse of the deglitched data signal to a threshold duration, and identify the pulse as representing a logic one based on the duration of the pulse exceeding the threshold duration.
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公开(公告)号：US20200036373A1
公开(公告)日：2020-01-30
申请号：US16353853
申请日：2019-03-14
Applicant: Texas Instruments Incorporated
Inventor： David Wayne Evans , Kavitha Rapolu
IPC: H03K17/082
Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to improve switching conditions in a closed loop system. An example device includes a first switch adapted to be coupled to a first node, a second switch adapted to be coupled to a second node, a capacitor including a first terminal and a second terminal, wherein the first terminal is coupled the first switch, and wherein the second terminal is coupled to the second switch, a first multiplier coupled to the first terminal and to the second terminal, wherein the first multiplier is adapted to be coupled to at least a third node and a fourth node, and a second multiplier coupled to the first terminal and to the second terminal.
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公开(公告)号：US20210096592A1
公开(公告)日：2021-04-01
申请号：US17039260
申请日：2020-09-30
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Michael Ryan Hanschke , Pankaj Pandey , Joseph Pham , David Wayne Evans
Abstract: A clock data recovery circuit includes a deglitch filter circuit and a timer circuit. The deglitch filter circuit is configured to remove pulses of less than a predetermined duration from a data signal to produce a deglitched data signal. The timer circuit is coupled to the deglitch filter, and is configured to compare a duration of a pulse of the deglitched data signal to a threshold duration, and identify the pulse as representing a logic one based on the duration of the pulse exceeding the threshold duration.
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公开(公告)号：US10707857B2
公开(公告)日：2020-07-07
申请号：US16353853
申请日：2019-03-14
Applicant: Texas Instruments Incorporated
Inventor： David Wayne Evans , Kavitha Rapolu
IPC: H03K17/082 , H03M1/08 , H03K17/08
Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to improve switching conditions in a closed loop system. An example device includes a first switch adapted to be coupled to a first node, a second switch adapted to be coupled to a second node, a capacitor including a first terminal and a second terminal, wherein the first terminal is coupled the first switch, and wherein the second terminal is coupled to the second switch, a first multiplier coupled to the first terminal and to the second terminal, wherein the first multiplier is adapted to be coupled to at least a third node and a fourth node, and a second multiplier coupled to the first terminal and to the second terminal.
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公开(公告)号：US11994901B2
公开(公告)日：2024-05-28
申请号：US17841255
申请日：2022-06-15
Applicant: Texas Instruments Incorporated
Inventor： Michael Ryan Hanschke , Pankaj Pandey , Joseph Pham , David Wayne Evans
CPC classification number: G06F1/14 , G06F11/1604 , H04L7/0037 , H04L7/0045
Abstract: A clock data recovery circuit includes a deglitch filter circuit and a timer circuit. The deglitch filter circuit is configured to remove pulses of less than a particular duration from a data signal to produce a deglitched data signal. The timer circuit is coupled to the deglitch filter, and is configured to compare a duration of a pulse of the deglitched data signal to a threshold duration, and identify the pulse as representing a logic one based on the duration of the pulse exceeding the threshold duration.
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Patent Agency Ranking
公开(公告)号：US11385677B2
公开(公告)日：2022-07-12
申请号：US17039260
申请日：2020-09-30
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Michael Ryan Hanschke , Pankaj Pandey , Joseph Pham , David Wayne Evans
Abstract: A clock data recovery circuit includes a deglitch filter circuit and a timer circuit. The deglitch filter circuit is configured to remove pulses of less than a predetermined duration from a data signal to produce a deglitched data signal. The timer circuit is coupled to the deglitch filter, and is configured to compare a duration of a pulse of the deglitched data signal to a threshold duration, and identify the pulse as representing a logic one based on the duration of the pulse exceeding the threshold duration.
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公开(公告)号：US20200336139A1
公开(公告)日：2020-10-22
申请号：US16921552
申请日：2020-07-06
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： David Wayne Evans , Kavitha Rapolu
IPC: H03K17/082
Abstract: A device includes: a capacitor having first and second terminals; a first switch; a second switch coupled to the second terminal; a first multiplier coupled between the first and second terminals; a second multiplier coupled between the first and second terminals; and a buffer having an input terminal and an output terminal. The first switch is coupled between the output terminal and the first terminal.
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公开(公告)号：US10044271B1
公开(公告)日：2018-08-07
申请号：US15581747
申请日：2017-04-28
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Rida Shawky Assaad , David Wayne Evans
Abstract: Methods and apparatus for DC-DC soft start are disclosed herein, an example DC-DC voltage converter includes at least two transistors to at least charge or discharge an inductor from an input source and to ground respectively, the inductor to output an output voltage. A synchronize and track circuit generates a bias current based on a reference voltage. An amplifier generates an error current based on an output voltage and the reference voltage. An oscillator oscillates at a switching frequency based on the bias current and the error current. A multiplexer selects between (1) a first input signal generated based on the switching frequency, and (2) a second input signal generated based on the switching frequency and the error current, for output as a reset signal. A latch provides a control signal to the at least two transistors based on the reset signal and the switching frequency.
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公开(公告)号：US20220308618A1
公开(公告)日：2022-09-29
申请号：US17841255
申请日：2022-06-15
Applicant: Texas Instruments Incorporated
Inventor： Michael Ryan Hanschke , Pankaj Pandey , Joseph Pham , David Wayne Evans
Abstract: A clock data recovery circuit includes a deglitch filter circuit and a timer circuit. The deglitch filter circuit is configured to remove pulses of less than a particular duration from a data signal to produce a deglitched data signal. The timer circuit is coupled to the deglitch filter, and is configured to compare a duration of a pulse of the deglitched data signal to a threshold duration, and identify the pulse as representing a logic one based on the duration of the pulse exceeding the threshold duration.
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公开(公告)号：US11218146B2
公开(公告)日：2022-01-04
申请号：US16921552
申请日：2020-07-06
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： David Wayne Evans , Kavitha Rapolu
IPC: H03K17/082 , H03K17/08 , H03M1/08
Abstract: A device includes: a capacitor having first and second terminals; a first switch; a second switch coupled to the second terminal; a first multiplier coupled between the first and second terminals; a second multiplier coupled between the first and second terminals; and a buffer having an input terminal and an output terminal. The first switch is coupled between the output terminal and the first terminal.
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