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公开(公告)号：US20210096592A1
公开(公告)日：2021-04-01
申请号：US17039260
申请日：2020-09-30
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Michael Ryan Hanschke , Pankaj Pandey , Joseph Pham , David Wayne Evans
Abstract: A clock data recovery circuit includes a deglitch filter circuit and a timer circuit. The deglitch filter circuit is configured to remove pulses of less than a predetermined duration from a data signal to produce a deglitched data signal. The timer circuit is coupled to the deglitch filter, and is configured to compare a duration of a pulse of the deglitched data signal to a threshold duration, and identify the pulse as representing a logic one based on the duration of the pulse exceeding the threshold duration.
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公开(公告)号：US20240272670A1
公开(公告)日：2024-08-15
申请号：US18645579
申请日：2024-04-25
Applicant: Texas Instruments Incorporated
Inventor： Michael Ryan Hanschke , Pankaj Pandey , Joseph Pham , David Wayne Evans
CPC classification number: G06F1/14 , G06F11/1604 , H04L7/0037 , H04L7/0045
Abstract: A clock data recovery circuit includes a deglitch filter circuit and a timer circuit. The deglitch filter circuit is configured to remove pulses of less than a particular duration from a data signal to produce a deglitched data signal. The timer circuit is coupled to the deglitch filter, and is configured to compare a duration of a pulse of the deglitched data signal to a threshold duration, and identify the pulse as representing a logic one based on the duration of the pulse exceeding the threshold duration.
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公开(公告)号：US08896950B1
公开(公告)日：2014-11-25
申请号：US14295113
申请日：2014-06-03
Applicant: Texas Instruments Incorporated
Inventor： Arup Polley , Pankaj Pandey , Bryan Bloodworth
CPC classification number: G11B5/6011
Abstract: A circuit includes an input that receives a current that increases as a tunneling current sensor moves closer to a media. A high gain path is operatively coupled to the input to amplify the received current as a first amplified output. The first amplified output increases until a saturation threshold is attained for the high gain path. Further increases in the received current beyond the saturation threshold are diverted from the input as an overflow current. A low gain path is operatively coupled to the input to amplify the overflow current as a second amplified output. The second amplified output increases with the overflow current as the tunneling current sensor continues to move closer to the media.
Abstract translation: 电路包括接收当隧道电流传感器更靠近介质移动时增加的电流的输入。 高增益路径可操作地耦合到输入端，以将接收电流放大为第一放大输出。 第一个放大的输出增加，直到达到高增益路径的饱和阈值。 超过饱和阈值的接收电流的进一步增加作为溢出电流从输入转移。 低增益路径可操作地耦合到输入端以放大溢出电流作为第二放大输出。 随着隧道电流传感器继续移动到介质附近，第二个放大输出随溢流电流而增加。
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公开(公告)号：US20220308618A1
公开(公告)日：2022-09-29
申请号：US17841255
申请日：2022-06-15
Applicant: Texas Instruments Incorporated
Inventor： Michael Ryan Hanschke , Pankaj Pandey , Joseph Pham , David Wayne Evans
Abstract: A clock data recovery circuit includes a deglitch filter circuit and a timer circuit. The deglitch filter circuit is configured to remove pulses of less than a particular duration from a data signal to produce a deglitched data signal. The timer circuit is coupled to the deglitch filter, and is configured to compare a duration of a pulse of the deglitched data signal to a threshold duration, and identify the pulse as representing a logic one based on the duration of the pulse exceeding the threshold duration.
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Patent Agency Ranking
公开(公告)号：US20140368944A1
公开(公告)日：2014-12-18
申请号：US14295113
申请日：2014-06-03
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： ARUP POLLEY , Pankaj Pandey , Bryan Bloodworth
CPC classification number: G11B5/6011
Abstract: A circuit includes an input that receives a current that increases as a tunneling current sensor moves closer to a media. A high gain path is operatively coupled to the input to amplify the received current as a first amplified output. The first amplified output increases until a saturation threshold is attained for the high gain path. Further increases in the received current beyond the saturation threshold are diverted from the input as an overflow current. A low gain path is operatively coupled to the input to amplify the overflow current as a second amplified output. The second amplified output increases with the overflow current as the tunneling current sensor continues to move closer to the media.
Abstract translation: 电路包括接收当隧道电流传感器更靠近介质移动时增加的电流的输入。 高增益路径可操作地耦合到输入端，以将接收电流放大为第一放大输出。 第一个放大的输出增加，直到达到高增益路径的饱和阈值。 超过饱和阈值的接收电流的进一步增加作为溢出电流从输入转移。 低增益路径可操作地耦合到输入端以放大溢出电流作为第二放大输出。 随着隧道电流传感器继续移动到介质附近，第二个放大输出随溢流电流而增加。
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公开(公告)号：US11994901B2
公开(公告)日：2024-05-28
申请号：US17841255
申请日：2022-06-15
Applicant: Texas Instruments Incorporated
Inventor： Michael Ryan Hanschke , Pankaj Pandey , Joseph Pham , David Wayne Evans
CPC classification number: G06F1/14 , G06F11/1604 , H04L7/0037 , H04L7/0045
Abstract: A clock data recovery circuit includes a deglitch filter circuit and a timer circuit. The deglitch filter circuit is configured to remove pulses of less than a particular duration from a data signal to produce a deglitched data signal. The timer circuit is coupled to the deglitch filter, and is configured to compare a duration of a pulse of the deglitched data signal to a threshold duration, and identify the pulse as representing a logic one based on the duration of the pulse exceeding the threshold duration.
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公开(公告)号：US11385677B2
公开(公告)日：2022-07-12
申请号：US17039260
申请日：2020-09-30
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Michael Ryan Hanschke , Pankaj Pandey , Joseph Pham , David Wayne Evans
Abstract: A clock data recovery circuit includes a deglitch filter circuit and a timer circuit. The deglitch filter circuit is configured to remove pulses of less than a predetermined duration from a data signal to produce a deglitched data signal. The timer circuit is coupled to the deglitch filter, and is configured to compare a duration of a pulse of the deglitched data signal to a threshold duration, and identify the pulse as representing a logic one based on the duration of the pulse exceeding the threshold duration.
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8.发明授权公开(公告)号：US11082052B2
公开(公告)日：2021-08-03
申请号：US16854584
申请日：2020-04-21
Applicant: Texas Instruments Incorporated
Inventor： Byungchul Jang , Adam Lee Shook , Pankaj Pandey
IPC: G06F1/04 , G06F3/041 , H03K3/00 , H03K3/012 , H03L7/099 , G05F1/59 , G05F1/575 , H03K17/687 , H03K17/567
Abstract: Frequency lock loop (FLL) circuits, low voltage dropout regulator circuits, and related methods are disclosed. An example gate driver integrated circuit includes a first die including a FLL circuit to generate a first clock signal having a first phase and a first frequency, a second clock signal having the first frequency and a second phase different from the first phase, and control a plurality of switching networks to increase the first frequency to a second frequency, and generate a feedback voltage based on the second frequency, and a second die coupled to the first die, the second die including a low dropout (LDO) circuit and a driver, the driver configured to control a transistor based on the first frequency, the second die configured to be coupled to the transistor, the LDO circuit to generate a pass-gate voltage based on an output current of the LDO circuit satisfying a current threshold.
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9.发明申请公开(公告)号：US20210111726A1
公开(公告)日：2021-04-15
申请号：US16854584
申请日：2020-04-21
Applicant: Texas Instruments Incorporated
Inventor： Byungchul Jang , Adam Lee Shook , Pankaj Pandey
IPC: H03L7/099 , G05F1/59 , H03K17/567 , H03K17/687 , G05F1/575
Abstract: Frequency lock loop (FLL) circuits, low voltage dropout regulator circuits, and related methods are disclosed. An example gate driver integrated circuit includes a first die including a FLL circuit to generate a first clock signal having a first phase and a first frequency, a second clock signal having the first frequency and a second phase different from the first phase, and control a plurality of switching networks to increase the first frequency to a second frequency, and generate a feedback voltage based on the second frequency, and a second die coupled to the first die, the second die including a low dropout (LDO) circuit and a driver, the driver configured to control a transistor based on the first frequency, the second die configured to be coupled to the transistor, the LDO circuit to generate a pass-gate voltage based on an output current of the LDO circuit satisfying a current threshold.
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