公开(公告)号：US08927385B2

公开(公告)日：2015-01-06

申请号：US13716424

申请日：2012-12-17

Applicant: Texas Instruments Incorporated

Inventor： Mahalingam Nandakumar ,  Deborah J. Riley ,  Amitabh Jain

IPC: H01L21/20 ,  H01L49/02 ,  H01L29/66 ,  H01L27/06

CPC classification number: H01L28/20 ,  H01L27/0629 ,  H01L29/66545

Abstract: An integrated circuit having a replacement gate MOS transistor and a polysilicon resistor may be formed by removing a portion at the top surface of the polysilicon layer in the resistor area. A subsequently formed gate etch hard mask includes a MOS hard mask segment over a MOS sacrificial gate and a resistor hard mask segment over a resistor body. The resistor body is thinner than the MOS sacrificial gate. During the gate replacement process sequence, the MOS hard mask segment is removed, exposing the MOS sacrificial gate while at least a portion of the resistor hard mask segment remains over the resistor body. The MOS sacrificial gate is replaced by a replacement gate while the resistor body is not replaced.

Abstract translation: 可以通过去除电阻器区域中的多晶硅层的顶表面的部分来形成具有替换栅极MOS晶体管和多晶硅电阻器的集成电路。 随后形成的栅极蚀刻硬掩模包括MOS牺牲栅极上的MOS硬掩模段和电阻体上的电阻器硬掩模段。 电阻体比MOS牺牲栅极薄。 在栅极替换处理序列期间，去除MOS硬掩模段，暴露MOS牺牲栅极，同时电阻器硬掩模段的至少一部分保留在电阻体上。 当不更换电阻体时，MOS牺牲栅极被替换栅极替代。

公开(公告)号：US20140167182A1

公开(公告)日：2014-06-19

申请号：US13716424

申请日：2012-12-17

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Mahalingam Nandakumar ,  Deborah J. Riley ,  Amitabh Jain

IPC: H01L49/02

CPC classification number: H01L28/20 ,  H01L27/0629 ,  H01L29/66545

Abstract: An integrated circuit having a replacement gate MOS transistor and a polysilicon resistor may be formed by removing a portion at the top surface of the polysilicon layer in the resistor area. A subsequently formed gate etch hard mask includes a MOS hard mask segment over a MOS sacrificial gate and a resistor hard mask segment over a resistor body. The resistor body is thinner than the MOS sacrificial gate. During the gate replacement process sequence, the MOS hard mask segment is removed, exposing the MOS sacrificial gate while at least a portion of the resistor hard mask segment remains over the resistor body. The MOS sacrificial gate is replaced by a replacement gate while the resistor body is not replaced.

Abstract translation: 可以通过去除电阻器区域中的多晶硅层的顶表面的部分来形成具有替换栅极MOS晶体管和多晶硅电阻器的集成电路。 随后形成的栅极蚀刻硬掩模包括MOS牺牲栅极上的MOS硬掩模段和电阻体上的电阻器硬掩模段。 电阻体比MOS牺牲栅极薄。 在栅极替换处理序列期间，去除MOS硬掩模段，暴露MOS牺牲栅极，同时电阻器硬掩模段的至少一部分保留在电阻体上。 当不更换电阻体时，MOS牺牲栅极被替换栅极替代。

公开(公告)号：US11417646B2

公开(公告)日：2022-08-16

申请号：US15172559

申请日：2016-06-03

Applicant: Texas Instruments Incorporated

Inventor： Manoj Mehrotra ,  Terry J. Bordelon ,  Deborah J. Riley

IPC: H01L27/092 ,  H01L27/06 ,  H01L21/8249 ,  H01L29/66 ,  H01L29/417 ,  H01L21/265 ,  H01L29/78 ,  H01L29/165 ,  H01L29/737 ,  H01L23/535 ,  H01L29/10 ,  H01L29/161

Abstract: An integrated circuit formed on a silicon substrate includes an NMOS transistor with n-channel raised source and drain (NRSD) layers adjacent to a gate of the NMOS transistor, a PMOS transistor with SiGe stressors in the substrate adjacent to a gate of the PMOS transistor, and an NPN heterojunction bipolar transistor (NHBT) with a p-type SiGe base formed in the substrate and an n-type silicon emitter formed on the SiGe base. The SiGe stressors and the SiGe base are formed by silicon-germanium epitaxy. The NRSD layers and the silicon emitter are formed by silicon epitaxy.

公开(公告)号：US10026837B2

公开(公告)日：2018-07-17

申请号：US14845112

申请日：2015-09-03

Applicant: Texas Instruments Incorporated

Inventor： Younsung Choi ,  Deborah J. Riley

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/08 ,  H01L29/161 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/165

Abstract: An integrated circuit and method having a first PMOS transistor with extension and pocket implants and with SiGe source and drains and having a second PMOS transistor without extension and without pocket implants and with SiGe source and drains. The distance from the SiGe source and drains to the gate of the first PMOS transistor is greater than the distance from the SiGe source and drains to the gate of the second PMOS transistor and the turn on voltage of the first PMOS transistor is at least 50 mV higher than the turn on voltage of the second PMOS transistor.

公开(公告)号：US09385117B2

公开(公告)日：2016-07-05

申请号：US14573006

申请日：2014-12-17

Applicant: Texas Instruments Incorporated

Inventor： Manoj Mehrotra ,  Terry J. Bordelon, Jr. ,  Deborah J. Riley

IPC: H01L21/8248 ,  H01L27/06 ,  H01L21/8249 ,  H01L29/66 ,  H01L29/417 ,  H01L21/265 ,  H01L29/78 ,  H01L29/737 ,  H01L29/161 ,  H01L29/165

CPC classification number: H01L27/0623 ,  H01L21/265 ,  H01L21/26513 ,  H01L21/8249 ,  H01L23/535 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/165 ,  H01L29/41783 ,  H01L29/66242 ,  H01L29/66575 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/737 ,  H01L29/7378 ,  H01L29/7833 ,  H01L29/7834 ,  H01L29/7848 ,  H01L29/7849

Abstract: An integrated circuit formed on a silicon substrate includes an NMOS transistor with n-channel raised source and drain (NRSD) layers adjacent to a gate of the NMOS transistor, a PMOS transistor with SiGe stressors in the substrate adjacent to a gate of the PMOS transistor, and an NPN heterojunction bipolar transistor (NHBT) with a p-type SiGe base formed in the substrate and an n-type silicon emitter formed on the SiGe base. The SiGe stressors and the SiGe base are formed by silicon-germanium epitaxy. The NRSD layers and the silicon emitter are formed by silicon epitaxy.

Abstract translation: 形成在硅衬底上的集成电路包括具有与NMOS晶体管的栅极相邻的n沟道升高源极和漏极（NRSD）层的NMOS晶体管，在与PMOS晶体管的栅极相邻的衬底中具有SiGe应力的PMOS晶体管 ，以及在衬底中形成有p型SiGe基极的NPN异质结双极晶体管（NHBT）和形成在SiGe基底上的n型硅发射极。 SiGe应力源和SiGe基极由硅 - 锗外延形成。 NRSD层和硅发射体通过硅外延形成。