公开(公告)号：US10483261B2

公开(公告)日：2019-11-19

申请号：US15447795

申请日：2017-03-02

Applicant: Texas Instruments Incorporated

Inventor： Brian K. Kirkpatrick ,  Amitabh Jain

IPC: H01L29/772 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/66 ,  H01L29/78 ,  H01L29/417 ,  H01L29/423 ,  H01L29/778 ,  H01L21/02 ,  H01L21/3065 ,  H01L21/3105 ,  H01L21/311 ,  H01L29/161

Abstract: A method of fabricating an integrated circuit includes depositing a first dielectric material onto a semiconductor surface of a substrate having a gate stack thereon including a gate electrode on a gate dielectric. The first dielectric material is etched to form sidewall spacers on sidewalls of the gate stack. A top surface of the first dielectric material is chemically converted to a second dielectric material by adding at least one element to provide surface converted sidewall spacers. The second dielectric material is chemically bonded across a transition region to the first dielectric material.

公开(公告)号：US09245975B2

公开(公告)日：2016-01-26

申请号：US14487663

申请日：2014-09-16

Applicant: Texas Instruments Incorporated

Inventor： Kwan-Yong Lim ,  Stanley Seungchul Song ,  Amitabh Jain

IPC: H01L21/336 ,  H01L29/66 ,  H01L29/78 ,  H01L29/423 ,  H01L29/04

CPC classification number: H01L29/66666 ,  H01L29/045 ,  H01L29/4236 ,  H01L29/42364 ,  H01L29/66545 ,  H01L29/66621 ,  H01L29/7827 ,  H01L29/7834

Abstract: A metal-oxide-semiconductor transistor (MOS) and method of fabricating the same, in which the effective channel length is increased relative to the width of the gate electrode. A dummy gate electrode overlying dummy gate dielectric material is formed at the surface of the structure, with self-aligned source/drain regions, and dielectric spacers on the sidewalls of the dummy gate structure. The dummy gate dielectric underlies the sidewall spacers. Following removal of the dummy gate electrode and the underlying dummy gate dielectric material, including from under the spacers, a silicon etch is performed to form a recess in the underlying substrate. This etch is self-limiting on the undercut sides, due to the crystal orientation, relative to the etch of the bottom of the recess. The gate dielectric and gate electrode material are then deposited into the remaining void, for example to form a high-k metal gate MOS transistor.

Abstract translation: 一种金属氧化物半导体晶体管（MOS）及其制造方法，其中有效沟道长度相对于栅电极的宽度增加。 在结构的表面上形成覆盖虚拟栅极电介质材料的虚拟栅电极，在虚拟栅极结构的侧壁上具有自对准的源极/漏极区域和电介质间隔物。 虚拟栅极电介质位于侧壁间隔物的正下方。 在去除虚拟栅极电极和下面的虚拟栅极电介质材料之后，包括从间隔物下方进行硅蚀刻以在下面的衬底中形成凹陷。 由于相对于凹部底部的蚀刻的晶体取向，该蚀刻在底切侧上是自限制的。 然后将栅极电介质和栅电极材料沉积到剩余的空隙中，例如形成高k金属栅极MOS晶体管。

公开(公告)号：US08853042B2

公开(公告)日：2014-10-07

申请号：US14148840

申请日：2014-01-07

Applicant: Texas Instruments Incorporated

Inventor： Mahalingam Nandakumar ,  Amitabh Jain

IPC: H01L21/336 ,  H01L21/8234 ,  H01L29/66 ,  H01L21/28 ,  H01L29/78 ,  H01L21/265 ,  H01L29/10

CPC classification number: H01L21/823412 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/2658 ,  H01L21/26586 ,  H01L21/28202 ,  H01L21/823418 ,  H01L21/823462 ,  H01L29/1083 ,  H01L29/66537 ,  H01L29/6659 ,  H01L29/7833

Abstract: A method of forming an integrated circuit (IC) including a core and a non-core PMOS transistor includes forming a non-core gate structure including a gate electrode on a gate dielectric and a core gate structure including a gate electrode on a gate dielectric. The gate dielectric for the non-core gate structure is at least 2 Å of equivalent oxide thickness (EOT) thicker as compared to the gate dielectric for the core gate structure. P-type lightly doped drain (PLDD) implantation including boron establishes source/drain extension regions in the substrate.The PLDD implantation includes selective co-implanting of carbon and nitrogen into the source/drain extension region of the non-core gate structure. Source and drain implantation forms source/drain regions for the non-core and core gate structure, wherein the source/drain regions are distanced from the non-core and core gate structures further than their source/drain extension regions. Source/drain annealing is performed after source and drain implantation.

Abstract translation: 形成包括芯和非芯型PMOS晶体管的集成电路（IC）的方法包括在栅极电介质上形成包括栅电极的非核栅极结构和在栅极电介质上包括栅电极的芯栅极结构。 与核心栅极结构的栅极电介质相比，非核心栅极结构的栅极电介质至少为等效氧化物厚度（EOT）的2埃。 包括硼的P型轻掺杂漏极（PLDD）注入在衬底中建立源极/漏极延伸区域。 PLDD注入包括将碳和氮选择性共注入到非核栅极结构的源极/漏极延伸区域中。 源极和漏极注入形成用于非核和核栅极结构的源极/漏极区，其中源极/漏极区远离它们的源极/漏极延伸区域的非核心和核栅极结构。 在源极和漏极之间进行源极/漏极退火。

公开(公告)号：US20140159142A1

公开(公告)日：2014-06-12

申请号：US13707865

申请日：2012-12-07

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Kwan-Yong Lim ,  Stanley Seungchul Song ,  Amitabh Jain

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/66666 ,  H01L29/045 ,  H01L29/4236 ,  H01L29/42364 ,  H01L29/66545 ,  H01L29/66621 ,  H01L29/7827 ,  H01L29/7834

Abstract: A metal-oxide-semiconductor transistor (MOS) and method of fabricating the same, in which the effective channel length is increased relative to the width of the gate electrode. A dummy gate electrode overlying dummy gate dielectric material is formed at the surface of the structure, with self-aligned source/drain regions, and dielectric spacers on the sidewalls of the dummy gate structure. The dummy gate dielectric underlies the sidewall spacers. Following removal of the dummy gate electrode and the underlying dummy gate dielectric material, including from under the spacers, a silicon etch is performed to form a recess in the underlying substrate. This etch is self-limiting on the undercut sides, due to the crystal orientation, relative to the etch of the bottom of the recess. The gate dielectric and gate electrode material are then deposited into the remaining void, for example to form a high-k metal gate MOS transistor.

Abstract translation: 一种金属氧化物半导体晶体管（MOS）及其制造方法，其中有效沟道长度相对于栅电极的宽度增加。 在结构的表面上形成覆盖虚拟栅极电介质材料的虚拟栅电极，在虚拟栅极结构的侧壁上具有自对准的源极/漏极区域和电介质间隔物。 虚拟栅极电介质位于侧壁间隔物的正下方。 在去除虚拟栅极电极和下面的虚拟栅极电介质材料之后，包括从间隔物下方进行硅蚀刻以在下面的衬底中形成凹陷。 由于相对于凹部底部的蚀刻的晶体取向，该蚀刻在底切侧上是自限制的。 然后将栅极电介质和栅电极材料沉积到剩余的空隙中，例如形成高k金属栅极MOS晶体管。

公开(公告)号：US09620423B2

公开(公告)日：2017-04-11

申请号：US14878553

申请日：2015-10-08

Applicant: Texas Instruments Incorporated

Inventor： Brian K. Kirkpatrick ,  Amitabh Jain

IPC: H01L29/76 ,  H01L21/8238 ,  H01L29/66 ,  H01L29/78 ,  H01L29/417 ,  H01L29/423 ,  H01L29/778 ,  H01L21/02 ,  H01L21/3065 ,  H01L21/3105 ,  H01L21/311 ,  H01L27/092 ,  H01L29/161

CPC classification number: H01L27/092 ,  H01L21/0214 ,  H01L21/02167 ,  H01L21/3065 ,  H01L21/3105 ,  H01L21/31111 ,  H01L21/823864 ,  H01L29/161 ,  H01L29/41775 ,  H01L29/42364 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/778 ,  H01L29/7833

Abstract: A method of fabricating an integrated circuit includes depositing a first dielectric material onto a semiconductor surface of a substrate having a gate stack thereon including a gate electrode on a gate dielectric. The first dielectric material is etched to form sidewall spacers on sidewalls of the gate stack. A top surface of the first dielectric material is chemically converted to a second dielectric material by adding at least one element to provide surface converted sidewall spacers. The second dielectric material is chemically bonded across a transition region to the first dielectric material.

公开(公告)号：US20150037952A1

公开(公告)日：2015-02-05

申请号：US14487663

申请日：2014-09-16

Applicant: Texas Instruments Incorporated

Inventor： Kwan-Yong Lim ,  Stanley Seungchul Song ,  Amitabh Jain

IPC: H01L29/66 ,  H01L29/423

CPC classification number: H01L29/66666 ,  H01L29/045 ,  H01L29/4236 ,  H01L29/42364 ,  H01L29/66545 ,  H01L29/66621 ,  H01L29/7827 ,  H01L29/7834

Abstract: A metal-oxide-semiconductor transistor (MOS) and method of fabricating the same, in which the effective channel length is increased relative to the width of the gate electrode. A dummy gate electrode overlying dummy gate dielectric material is formed at the surface of the structure, with self-aligned source/drain regions, and dielectric spacers on the sidewalls of the dummy gate structure. The dummy gate dielectric underlies the sidewall spacers. Following removal of the dummy gate electrode and the underlying dummy gate dielectric material, including from under the spacers, a silicon etch is performed to form a recess in the underlying substrate. This etch is self-limiting on the undercut sides, due to the crystal orientation, relative to the etch of the bottom of the recess. The gate dielectric and gate electrode material are then deposited into the remaining void, for example to form a high-k metal gate MOS transistor.

Abstract translation: 一种金属氧化物半导体晶体管（MOS）及其制造方法，其中有效沟道长度相对于栅电极的宽度增加。 在结构的表面上形成覆盖虚拟栅极电介质材料的虚拟栅电极，在虚拟栅极结构的侧壁上具有自对准的源极/漏极区域和电介质间隔物。 虚拟栅极电介质位于侧壁间隔物的正下方。 在去除虚拟栅极电极和下面的虚拟栅极电介质材料之后，包括从间隔物下方进行硅蚀刻以在下面的衬底中形成凹陷。 由于相对于凹部底部的蚀刻的晶体取向，该蚀刻在底切侧上是自限制的。 然后将栅极电介质和栅电极材料沉积到剩余的空隙中，例如形成高k金属栅极MOS晶体管。

公开(公告)号：US08927385B2

公开(公告)日：2015-01-06

申请号：US13716424

申请日：2012-12-17

Applicant: Texas Instruments Incorporated

Inventor： Mahalingam Nandakumar ,  Deborah J. Riley ,  Amitabh Jain

IPC: H01L21/20 ,  H01L49/02 ,  H01L29/66 ,  H01L27/06

CPC classification number: H01L28/20 ,  H01L27/0629 ,  H01L29/66545

Abstract: An integrated circuit having a replacement gate MOS transistor and a polysilicon resistor may be formed by removing a portion at the top surface of the polysilicon layer in the resistor area. A subsequently formed gate etch hard mask includes a MOS hard mask segment over a MOS sacrificial gate and a resistor hard mask segment over a resistor body. The resistor body is thinner than the MOS sacrificial gate. During the gate replacement process sequence, the MOS hard mask segment is removed, exposing the MOS sacrificial gate while at least a portion of the resistor hard mask segment remains over the resistor body. The MOS sacrificial gate is replaced by a replacement gate while the resistor body is not replaced.

Abstract translation: 可以通过去除电阻器区域中的多晶硅层的顶表面的部分来形成具有替换栅极MOS晶体管和多晶硅电阻器的集成电路。 随后形成的栅极蚀刻硬掩模包括MOS牺牲栅极上的MOS硬掩模段和电阻体上的电阻器硬掩模段。 电阻体比MOS牺牲栅极薄。 在栅极替换处理序列期间，去除MOS硬掩模段，暴露MOS牺牲栅极，同时电阻器硬掩模段的至少一部分保留在电阻体上。 当不更换电阻体时，MOS牺牲栅极被替换栅极替代。

公开(公告)号：US20140167182A1

公开(公告)日：2014-06-19

申请号：US13716424

申请日：2012-12-17

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Mahalingam Nandakumar ,  Deborah J. Riley ,  Amitabh Jain

IPC: H01L49/02

CPC classification number: H01L28/20 ,  H01L27/0629 ,  H01L29/66545

Abstract: An integrated circuit having a replacement gate MOS transistor and a polysilicon resistor may be formed by removing a portion at the top surface of the polysilicon layer in the resistor area. A subsequently formed gate etch hard mask includes a MOS hard mask segment over a MOS sacrificial gate and a resistor hard mask segment over a resistor body. The resistor body is thinner than the MOS sacrificial gate. During the gate replacement process sequence, the MOS hard mask segment is removed, exposing the MOS sacrificial gate while at least a portion of the resistor hard mask segment remains over the resistor body. The MOS sacrificial gate is replaced by a replacement gate while the resistor body is not replaced.

Abstract translation: 可以通过去除电阻器区域中的多晶硅层的顶表面的部分来形成具有替换栅极MOS晶体管和多晶硅电阻器的集成电路。 随后形成的栅极蚀刻硬掩模包括MOS牺牲栅极上的MOS硬掩模段和电阻体上的电阻器硬掩模段。 电阻体比MOS牺牲栅极薄。 在栅极替换处理序列期间，去除MOS硬掩模段，暴露MOS牺牲栅极，同时电阻器硬掩模段的至少一部分保留在电阻体上。 当不更换电阻体时，MOS牺牲栅极被替换栅极替代。

公开(公告)号：US10068802B2

公开(公告)日：2018-09-04

申请号：US13654161

申请日：2012-10-17

Applicant: Texas Instruments Incorporated

Inventor： Ebenezer Eshun ,  Himadri Sekhar Pal ,  Amitabh Jain

IPC: H01L21/8234 ,  H01L21/265 ,  H01L29/66 ,  H01L29/78

Abstract: An integrated circuit containing MOS transistors may be formed using a split carbon co-implantation. The split carbon co-implant includes an angled carbon implant and a zero-degree carbon implant that is substantially perpendicular to a top surface of the integrated circuit. The split carbon co-implant is done at the LDD and halo implant steps.

公开(公告)号：US09024384B2

公开(公告)日：2015-05-05

申请号：US14025920

申请日：2013-09-13

Applicant: Texas Instruments Incorporated

Inventor： Mahalingam Nandakumar ,  Amitabh Jain

IPC: H01L29/66 ,  H01L21/265 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/78

CPC classification number: H01L29/6659 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/823418 ,  H01L21/823814 ,  H01L29/66477 ,  H01L29/7833

Abstract: A method of forming an integrated circuit (IC) having at least one PMOS transistor includes performing PLDD implantation including co-implanting indium, carbon and a halogen, and a boron specie to establish source/drain extension regions in a substrate having a semiconductor surface on either side of a gate structure including a gate electrode on a gate dielectric formed on the semiconductor surface. Source and drain implantation is performed to establish source/drain regions, wherein the source/drain regions are distanced from the gate structure further than the source/drain extension regions. Source/drain annealing is performed after the source and drain implantation. The co-implants can be selectively provided to only core PMOS transistors, and the method can include a ultra high temperature anneal such as a laser anneal after the PLDD implantation.

Abstract translation: 形成具有至少一个PMOS晶体管的集成电路（IC）的方法包括执行PLDD注入，包括共注入铟，碳和卤素，以及硼物种，以在具有半导体表面的衬底中建立源极/漏极延伸区域 栅极结构的任一侧包括形成在半导体表面上的栅极电介质上的栅电极。 进行源极和漏极注入以建立源极/漏极区域，其中源极/漏极区域远离源极/漏极延伸区域远离栅极结构。 在源极和漏极注入之后进行源极/漏极退火。 共注入物可以选择性地仅提供到核心PMOS晶体管，并且该方法可以包括超高温退火，例如在PLDD注入之后的激光退火。