公开(公告)号：US10608538B1

公开(公告)日：2020-03-31

申请号：US16258320

申请日：2019-01-25

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Manuel Wiersch ,  Gerhard Thiele

IPC: H02M3/158 ,  H02M1/08 ,  H03K17/687 ,  H02M3/157

Abstract: A device includes a first transistor coupled to a ground node and a current source. The first transistor includes a control terminal coupled to a reference voltage source, where the current source is coupled to an input voltage source. The device includes a second transistor coupled to the input voltage source, where the second transistor includes a control terminal coupled to the first transistor. The device includes a third transistor coupled to the second transistor, where the third transistor includes a control terminal coupled to an output voltage node. The device includes a fourth transistor coupled to the third transistor, where the fourth transistor includes a control terminal coupled to the output voltage node. The device includes a fifth transistor coupled to the fourth transistor and a resistor, where the fifth transistor includes a control terminal coupled to the fourth transistor. The resistor is coupled to the ground node.

公开(公告)号：US20240210982A1

公开(公告)日：2024-06-27

申请号：US18171006

申请日：2023-02-17

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Manuel Wiersch ,  Ferdinand Stettner

IPC: G05F3/26

CPC classification number: G05F3/262

Abstract: A circuit for controlling a discharge transistor for a power stage includes a current mirror, a first diode, and a second diode. The current mirror includes first, second, third and fourth field-effect transistors (FETs) configured to provide a fast startup signal and a startup discharge signal. The startup discharge signal is provided to a gate of the discharge transistor. The first diode is configured to limit the fast startup signal to a first maximum voltage less than the supply voltage, and the second diode is configured to limit the startup discharge signal to a second maximum voltage less than the supply voltage.

公开(公告)号：US11804769B2

公开(公告)日：2023-10-31

申请号：US17138603

申请日：2020-12-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Eduardas Jodka ,  Gaetano Maria Walter Petrina ,  Manuel Wiersch

IPC: H02M1/08 ,  H02M1/44 ,  H03K17/687 ,  H03K17/16

CPC classification number: H02M1/08 ,  H02M1/44 ,  H03K17/161 ,  H03K17/687

Abstract: In some examples, an apparatus includes a driver having a driver output, a capacitor having a first plate and a second plate, the first plate coupled to the driver output, and a transistor having a transistor gate, a transistor source, and a transistor drain. The apparatus also includes a first switch coupled between the second plate and the transistor gate, a second switch coupled between the second plate and the transistor drain, and a third switch coupled between the transistor gate and the transistor drain.

公开(公告)号：US12132402B2

公开(公告)日：2024-10-29

申请号：US18480074

申请日：2023-10-03

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Manuel Wiersch ,  Gerhard Thiele ,  Antonio Priego ,  Johann Erich Bayer

IPC: H02M3/158 ,  H02M1/00

CPC classification number: H02M3/158 ,  H02M1/0032 ,  H02M1/0048

Abstract: An electrical system includes: 1) a buck converter; 2) a battery coupled to an input of the buck converter; and 3) a load coupled to an output of the buck converter. The buck converter includes a high-side switch, a low-side switch, and regulation loop circuitry coupled to the high-side switch and the low-side switch. The regulation loop circuitry includes: 1) a main comparator; 2) a bias current source coupled to the main comparator and configured to provide a bias current to the main comparator; and 3) a dynamic biasing circuit coupled to the main comparator and configured to add a supplemental bias current to the bias current in 100% mode of the buck converter. The supplemental bias current varies depending on an input voltage (VIN) and an output voltage (VOUT) of the buck converter.

公开(公告)号：US11881780B2

公开(公告)日：2024-01-23

申请号：US18173859

申请日：2023-02-24

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Manuel Wiersch ,  Gerhard Thiele ,  Antonio Priego ,  Johann Erich Bayer

IPC: H02M3/158 ,  H02M1/00

CPC classification number: H02M3/158 ,  H02M1/0032 ,  H02M1/0048

Abstract: An electrical system includes: 1) a buck converter; 2) a battery coupled to an input of the buck converter; and 3) a load coupled to an output of the buck converter. The buck converter includes a high-side switch, a low-side switch, and regulation loop circuitry coupled to the high-side switch and the low-side switch. The regulation loop circuitry includes: 1) a main comparator; 2) a bias current source coupled to the main comparator and configured to provide a bias current to the main comparator; and 3) a dynamic biasing circuit coupled to the main comparator and configured to add a supplemental bias current to the bias current in 100% mode of the buck converter. The supplemental bias current varies depending on an input voltage (VIN) and an output voltage (VOUT) of the buck converter.

公开(公告)号：US11784568B2

公开(公告)日：2023-10-10

申请号：US16585168

申请日：2019-09-27

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Antonio Priego ,  Gerhard Thiele ,  Manuel Wiersch ,  Johann Erich Bayer

IPC: H02M3/158 ,  H02M1/00

CPC classification number: H02M3/1582 ,  H02M1/0061 ,  H02M1/0003

Abstract: A switching converter circuit includes a voltage regulation loop configured to provide an output voltage (VOUT) based on an input voltage (VIN). The switching converter circuit also includes a 100% mode circuitry coupled to the voltage regulation loop, wherein the 100% mode circuitry is configured to apply an offset to VOUT in response to detecting that VIN is approaching VOUT.

公开(公告)号：US11616439B2

公开(公告)日：2023-03-28

申请号：US16590021

申请日：2019-10-01

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Manuel Wiersch ,  Gerhard Thiele ,  Antonio Priego ,  Johann Erich Bayer

IPC: H02M3/158 ,  H02M1/00

Abstract: An electrical system includes: 1) a buck converter; 2) a battery coupled to an input of the buck converter; and 3) a load coupled to an output of the buck converter. The buck converter includes a high-side switch, a low-side switch, and regulation loop circuitry coupled to the high-side switch and the low-side switch. The regulation loop circuitry includes: 1) a main comparator; 2) a bias current source coupled to the main comparator and configured to provide a bias current to the main comparator; and 3) a dynamic biasing circuit coupled to the main comparator and configured to add a supplemental bias current to the bias current in 100% mode of the buck converter. The supplemental bias current varies depending on an input voltage (VIN) and an output voltage (VOUT) of the buck converter.

公开(公告)号：US10992229B2

公开(公告)日：2021-04-27

申请号：US16655876

申请日：2019-10-17

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Gerhard Thiele ,  Manuel Wiersch ,  Antonio Priego ,  Johann Erich Bayer ,  Stefan Herzer

IPC: H02M3/156 ,  H02M1/00 ,  H02M3/158

Abstract: An electrical system includes: 1) a buck converter; 2) a battery coupled to an input of the buck converter; and 3) a load coupled to an output of the buck converter. The buck converter includes a high-side switch, a low-side switch, and regulation loop circuitry coupled to the high-side switch and the low-side switch. The regulation loop circuitry includes a comparator with preamplifier gain adjustment circuitry configured to adjust a preamplifier gain of the comparator based on an overdrive voltage.

公开(公告)号：US10965216B2

公开(公告)日：2021-03-30

申请号：US16141063

申请日：2018-09-25

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Gerhard Thiele ,  Manuel Wiersch

IPC: H02M3/158 ,  H02M1/08 ,  H02M1/00

Abstract: An integrated circuit comprising: a high-side pMOSFET comprising a drain and a gate; a node coupled to the drain of the high-side pMOSFET; a voltage-to-current circuit comprising a first nMOSFET and a first resistor, the first nMOSFET comprising a gate and a source, the first resistor comprising a terminal coupled to the source of the first nMOSFET; an error amplifier comprising an output port coupled to the gate of the first nMOSFET; a skip clamp nMOSFET comprising a source coupled to the output port of the error amplifier; and a current limit clamp pMOSFET comprising a source coupled to the output port of the error amplifier.