公开(公告)号：US20240113156A1

公开(公告)日：2024-04-04

申请号：US17957983

申请日：2022-09-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Scott William JESSEN ,  Steven Lee PRINS ,  Sameer Prakash PENDHARKAR ,  Abbas ALI ,  Gregory Boyd SHINN

IPC: H01L49/02 ,  H01L27/06

CPC classification number: H01L28/24 ,  H01L27/0629 ,  H01L21/0274

Abstract: A passive circuit component includes an edge having a low line edge roughness (LER). A method for manufacturing the passive circuit component includes a self-aligned double patterning (SADP) etch process using a tri-layer process flow. The tri-layer process flow includes use of an underlayer, hard mask, and photoresist. The passive circuit component made by this method achieves improved mismatch between like components due to the low LER.

公开(公告)号：US20200381358A1

公开(公告)日：2020-12-03

申请号：US16995288

申请日：2020-08-17

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Qi-Zhong HONG ,  Honglin GUO ,  Benjamin James Timmer ,  Gregory Boyd SHINN

IPC: H01L23/522 ,  H01L49/02

Abstract: An integrated circuit (IC) includes a substrate having a semiconductor surface layer with functional circuitry for realizing at least one circuit function, with an inter level dielectric (ILD) layer on a metal layer that is above the semiconductor surface layer. A thin film resistor (TFR) including a TFR layer is on the ILD layer. At least one vertical metal wall is on at least two sides of the TFR. The metal walls include at least 2 metal levels coupled by filled vias. The functional circuitry is outside the metal walls.