公开(公告)号：US20210280702A1

公开(公告)日：2021-09-09

申请号：US17330012

申请日：2021-05-25

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Chang Soo SUH ,  Sameer Prakash PENDHARKAR ,  Naveen TIPIRNENI ,  Jungwoo JOH

IPC: H01L29/778 ,  H01L29/66 ,  H01L29/20 ,  H01L29/423 ,  H01L21/308 ,  H01L29/417 ,  H01L21/02

Abstract: In some examples, a gallium nitride (GaN)-based transistor, comprises a substrate; a GaN layer supported by the substrate; an aluminum nitride gallium (AlGaN) layer supported by the GaN layer; a p-doped GaN structure supported by the AlGaN layer; and multiple p-doped GaN blocks supported by the AlGaN layer, each of the multiple p-doped GaN blocks physically separated from the remaining multiple p-doped GaN blocks, wherein first and second contours of a two-dimensional electron gas (2DEG) of the GaN-based transistor are at an interface of the AlGaN and GaN layers.

公开(公告)号：US20240113156A1

公开(公告)日：2024-04-04

申请号：US17957983

申请日：2022-09-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Scott William JESSEN ,  Steven Lee PRINS ,  Sameer Prakash PENDHARKAR ,  Abbas ALI ,  Gregory Boyd SHINN

IPC: H01L49/02 ,  H01L27/06

CPC classification number: H01L28/24 ,  H01L27/0629 ,  H01L21/0274

Abstract: A passive circuit component includes an edge having a low line edge roughness (LER). A method for manufacturing the passive circuit component includes a self-aligned double patterning (SADP) etch process using a tri-layer process flow. The tri-layer process flow includes use of an underlayer, hard mask, and photoresist. The passive circuit component made by this method achieves improved mismatch between like components due to the low LER.

公开(公告)号：US20200287033A1

公开(公告)日：2020-09-10

申请号：US16294687

申请日：2019-03-06

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Chang Soo SUH ,  Sameer Prakash PENDHARKAR ,  Naveen TIPIRNENI ,  Jungwoo JOH

IPC: H01L29/778 ,  H01L29/66 ,  H01L29/20 ,  H01L21/02 ,  H01L21/308 ,  H01L29/417 ,  H01L29/423

Abstract: In some examples, a gallium nitride (GaN)-based transistor, comprises a substrate; a GaN layer supported by the substrate; an aluminum nitride gallium (AlGaN) layer supported by the GaN layer; a p-doped GaN structure supported by the AlGaN layer; and multiple p-doped GaN blocks supported by the AlGaN layer, each of the multiple p-doped GaN blocks physically separated from the remaining multiple p-doped GaN blocks, wherein first and second contours of a two-dimensional electron gas (2DEG) of the GaN-based transistor are at an interface of the AlGaN and GaN layers.