公开(公告)号：US11699649B2

公开(公告)日：2023-07-11

申请号：US17525412

申请日：2021-11-12

Applicant: Texas Instruments Incorporated

Inventor： Chang-Yen Ko ,  J K Ho

IPC: H01L21/00 ,  H01L23/50 ,  H01L23/28 ,  H01L23/495 ,  H01L23/00

CPC classification number: H01L23/50 ,  H01L23/28 ,  H01L23/49513 ,  H01L23/49575 ,  H01L24/32 ,  H01L24/49 ,  H01L2924/14

Abstract: An electronic device (e.g., integrated circuit) and method of making the electronic device is provided that reduces a strength of an electric field generated outside a package of the electronic device proximate to the low voltage lead pins. The electronic device includes a low voltage side and a high voltage side. The low voltage side includes a low voltage die attached to a low voltage die attach pad. Similarly, the high voltage side includes a high voltage die attached to a high voltage die attach pad. Lead pins are attached to each of the low and high voltage attach pads and extend out from a package of the electronic device in an inverted direction.

公开(公告)号：US11081429B2

公开(公告)日：2021-08-03

申请号：US16600615

申请日：2019-10-14

Applicant: Texas Instruments Incorporated

Inventor： Jason Chien ,  J K Ho ,  Yuh-Harng Chien

IPC: H01L23/495 ,  H01L21/00 ,  H01L23/48 ,  H01L23/498 ,  H01L23/00

Abstract: A packaged semiconductor device includes a leadframe including a finger pad(s) that is integrated, and spans a finger pad area including a width narrower than its length. A first portion of the finger pad area provides a die support area. A second portion of the finger pad area provides a wire bond area including first and second wire bond pads on a first and second side of the die support area. One of the wire bond pads further includes a lead terminal integrally connected. The IC die has a top side with bond pads and a back side having a non-electrically conductive die attach material attached to the die support area. Bond wires extend from the bond pads to the first and second wire bond pads. A mold compound encapsulates the packaged semiconductor device leaving exposed at least the lead terminal on a bottom side of the packaged semiconductor device.

公开(公告)号：US11437303B2

公开(公告)日：2022-09-06

申请号：US16273152

申请日：2019-02-12

Applicant: Texas Instruments Incorporated

Inventor： Chang-Yen Ko ,  J K Ho

IPC: H01L23/495 ,  H01L23/00 ,  H01L21/82 ,  H01L23/31 ,  H01L23/64

Abstract: A microelectronic device has a substrate attached to a substrate pad on a first face of the substrate, and a component attached to the substrate on the first face. The substrate has a component placement guide on the first face. The substrate has a singulation guide on a second face of the substrate, located opposite from the first face. The microelectronic device is formed by attaching the component to a substrate sheet which contains the substrate. The substrate sheet with the component is mounted on a singulation film so that the component contacts the singulation film. The singulation guide on the second face of the substrate is located opposite from the singulation film. The substrate is singulated from the substrate sheet. The substrate with the component is attached to the substrate pad on the first face of the substrate, adjacent to the component.

公开(公告)号：US11183450B2

公开(公告)日：2021-11-23

申请号：US16892066

申请日：2020-06-03

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Chang-Yen Ko ,  J K Ho

IPC: H01L21/00 ,  H01L23/50 ,  H01L23/28 ,  H01L23/495 ,  H01L23/00

Abstract: An electronic device (e.g., integrated circuit) and method of making the electronic device is provided that reduces a strength of an electric field generated outside a package of the electronic device proximate to the low voltage lead pins. The electronic device includes a low voltage side and a high voltage side. The low voltage side includes a low voltage die attached to a low voltage die attach pad. Similarly, the high voltage side includes a high voltage die attached to a high voltage die attach pad. Lead pins are attached to each of the low and high voltage attach pads and extend out from a package of the electronic device in an inverted direction.

公开(公告)号：US11538740B2

公开(公告)日：2022-12-27

申请号：US16511313

申请日：2019-07-15

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jason Chien ,  Yuh-Harng Chien ,  J K Ho

IPC: H01L23/495 ,  H01L23/00 ,  H01L23/31 ,  H01L25/065

Abstract: A semiconductor package includes a first lead with first and second ends extending in the same direction as one another. At least one second lead has first and second ends and is partially surrounded by the first lead. A die pad is provided and a die is connected to the die pad. Wires electrically connect the die to the first lead and the at least one second lead. An insulating layer extends over the leads, the die pad, and the die such that the first end of the at least one second lead is exposed from the semiconductor package and the second end of the first lead is encapsulated entirely within the insulating layer.

公开(公告)号：US10714418B2

公开(公告)日：2020-07-14

申请号：US16137055

申请日：2018-09-20

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Chang-Yen Ko ,  J K Ho

IPC: H01L23/48 ,  H01L23/52 ,  H01L21/44 ,  H01L21/48 ,  H01L21/50 ,  H01L23/50 ,  H01L23/28 ,  H01L23/495 ,  H01L23/00

Abstract: An electronic device (e.g., integrated circuit) and method of making the electronic device is provided that reduces a strength of an electric field generated outside a package of the electronic device proximate to the low voltage lead pins. The electronic device includes a low voltage side and a high voltage side. The low voltage side includes a low voltage die attached to a low voltage die attach pad. Similarly, the high voltage side includes a high voltage die attached to a high voltage die attach pad. Lead pins are attached to each of the low and high voltage attach pads and extend out from a package of the electronic device in an inverted direction.

公开(公告)号：US11935789B2

公开(公告)日：2024-03-19

申请号：US17903709

申请日：2022-09-06

Applicant: Texas Instruments Incorporated

Inventor： Chang-Yen Ko ,  J K Ho

IPC: H01L21/82 ,  H01L23/00 ,  H01L23/31 ,  H01L23/495 ,  H01L23/64

CPC classification number: H01L21/82 ,  H01L23/3121 ,  H01L23/49503 ,  H01L23/49548 ,  H01L23/49575 ,  H01L23/645 ,  H01L24/09 ,  H01L24/17 ,  H01L24/33 ,  H01L24/49 ,  H01L24/73

Abstract: A microelectronic device has a substrate attached to a substrate pad on a first face of the substrate, and a component attached to the substrate on the first face. The substrate has a component placement guide on the first face. The substrate has a singulation guide on a second face of the substrate, located opposite from the first face. The microelectronic device is formed by attaching the component to a substrate sheet which contains the substrate. The substrate sheet with the component is mounted on a singulation film so that the component contacts the singulation film. The singulation guide on the second face of the substrate is located opposite from the singulation film. The substrate is singulated from the substrate sheet. The substrate with the component is attached to the substrate pad on the first face of the substrate, adjacent to the component.

公开(公告)号：US20210111103A1

公开(公告)日：2021-04-15

申请号：US16600615

申请日：2019-10-14

Applicant: Texas Instruments Incorporated

Inventor： Jason Chien ,  J K Ho ,  Yuh-Harng Chien

IPC: H01L23/495 ,  H01L23/498 ,  H01L23/00

Abstract: A packaged semiconductor device includes a leadframe including a finger pad(s) that is integrated, and spans a finger pad area including a width narrower than its length. A first portion of the finger pad area provides a die support area. A second portion of the finger pad area provides a wire bond area including first and second wire bond pads on a first and second side of the die support area. One of the wire bond pads further includes a lead terminal integrally connected. The IC die has a top side with bond pads and a back side having a non-electrically conductive die attach material attached to the die support area. Bond wires extend from the bond pads to the first and second wire bond pads. A mold compound encapsulates the packaged semiconductor device leaving exposed at least the lead terminal on a bottom side of the packaged semiconductor device.

公开(公告)号：US20150108038A1

公开(公告)日：2015-04-23

申请号：US14060949

申请日：2013-10-23

Applicant: Texas Instruments Incorporated

Inventor： Randy Hsu ,  Shawn Wu ,  J K Ho ,  Debby Hsiao

IPC: B65D73/02 ,  H05K13/00

CPC classification number: H05K13/0084

Abstract: A new type of tape and reel tape based on the cover tape having projections extending from the bottom surface of the cover tape leaving a minimum of adhesive surface exposed to the surface mount die or packages contained in the pocket areas of the carrier tape.

Abstract translation: 一种基于覆盖带的新型的带卷带，其具有从盖带的底表面延伸的突起，留下暴露于表面安装模的最小粘合剂表面或容纳在载带的袋区中的包装。