公开(公告)号：US10218338B1

公开(公告)日：2019-02-26

申请号：US15782200

申请日：2017-10-12

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Nikolaus Klemmer ,  Chan Fernando ,  Jaimin Mehta ,  Srinadh Madhavapeddi ,  Hamid Safiri ,  Atul Kumar Jain

IPC: H03K3/84 ,  H03K5/1252 ,  H03K17/16

Abstract: Aperiodic clock generation with clock spur suppression is based on cascaded randomizers, such as for mixed signal devices. A clock generator circuit includes an input node to receive the input periodic clock signal having an input-clock frequency. A first randomizer circuit coupled to receive the input clock signal from the input node, to perform signal randomization to suppress spurious signal content associated with (a) the input clock signal, and (b) the first randomizer circuit, and to generate an intermediate clock signal. A second concatenated randomizer circuit is coupled to receive the intermediate clock signal, to perform signal randomization to suppress spurious signal content associated with (a) the intermediated clock signal, and (b) the second randomizer circuit, and to generate an aperiodic output clock signal having a pre-defined average output-clock frequency that is less than the input-clock frequency. Example randomizers are a delta-sigma divider and a pulse swallower (in any order).

公开(公告)号：US10536258B2

公开(公告)日：2020-01-14

申请号：US15996444

申请日：2018-06-02

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Hunsoo Choo ,  Hamid Safiri ,  Nikolaus Klemmer ,  Jaimin Mehta ,  Srinadh Madhavapeddi ,  Charles Kasimer Sestok ,  Vijayavardhan Baireddy

IPC: H04L7/00 ,  G06F1/10

Abstract: Multi-domain clock generation with skew compensation is based on free-running counters in each of the multiple clock domains. Multi-domain clock generation circuitry provides at least first and second domain clocks generated with randomization, each based on an input clock with an input clock frequency, the domain clocks having a relative clock skew that is varied over time in magnitude and direction. A first circuit in a first clock domain, configured for operation with the first domain clock, includes a first free-running counter with a pre-defined first selected roll-over count, to generate a first free-running count (N1(k)) based on the first domain clock. A second circuit in a second clock domain is configured for operation with the second domain clock, and includes a second free-running counter with a pre-defined second selected roll-over count, to generate a second free-running count (N2(k)) based on the second domain clock.

公开(公告)号：US20190372747A1

公开(公告)日：2019-12-05

申请号：US15996444

申请日：2018-06-02

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Hunsoo Choo ,  Hamid Safiri ,  Nikolaus Klemmer ,  Jaimin Mehta ,  Srinadh Madhavapeddi ,  Charles Kasimer Sestok ,  Vijayavardhan Baireddy

IPC: H04L7/00 ,  G06F1/10

Abstract: Multi-domain clock generation with skew compensation is based on free-running counters in each of the multiple clock domains. Multi-domain clock generation circuitry provides at least first and second domain clocks generated with randomization, each based on an input clock with an input clock frequency, the domain clocks having a relative clock skew that is varied over time in magnitude and direction. A first circuit in a first clock domain, configured for operation with the first domain clock, includes a first free-running counter with a pre-defined first selected roll-over count, to generate a first free-running count (N1(k)) based on the first domain clock. A second circuit in a second clock domain is configured for operation with the second domain clock, and includes a second free-running counter with a pre-defined second selected roll-over count, to generate a second free-running count (N2(k)) based on the second domain clock.