公开(公告)号：US10536258B2

公开(公告)日：2020-01-14

申请号：US15996444

申请日：2018-06-02

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Hunsoo Choo ,  Hamid Safiri ,  Nikolaus Klemmer ,  Jaimin Mehta ,  Srinadh Madhavapeddi ,  Charles Kasimer Sestok ,  Vijayavardhan Baireddy

IPC: H04L7/00 ,  G06F1/10

Abstract: Multi-domain clock generation with skew compensation is based on free-running counters in each of the multiple clock domains. Multi-domain clock generation circuitry provides at least first and second domain clocks generated with randomization, each based on an input clock with an input clock frequency, the domain clocks having a relative clock skew that is varied over time in magnitude and direction. A first circuit in a first clock domain, configured for operation with the first domain clock, includes a first free-running counter with a pre-defined first selected roll-over count, to generate a first free-running count (N1(k)) based on the first domain clock. A second circuit in a second clock domain is configured for operation with the second domain clock, and includes a second free-running counter with a pre-defined second selected roll-over count, to generate a second free-running count (N2(k)) based on the second domain clock.

公开(公告)号：US20190372747A1

公开(公告)日：2019-12-05

申请号：US15996444

申请日：2018-06-02

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Hunsoo Choo ,  Hamid Safiri ,  Nikolaus Klemmer ,  Jaimin Mehta ,  Srinadh Madhavapeddi ,  Charles Kasimer Sestok ,  Vijayavardhan Baireddy

IPC: H04L7/00 ,  G06F1/10

Abstract: Multi-domain clock generation with skew compensation is based on free-running counters in each of the multiple clock domains. Multi-domain clock generation circuitry provides at least first and second domain clocks generated with randomization, each based on an input clock with an input clock frequency, the domain clocks having a relative clock skew that is varied over time in magnitude and direction. A first circuit in a first clock domain, configured for operation with the first domain clock, includes a first free-running counter with a pre-defined first selected roll-over count, to generate a first free-running count (N1(k)) based on the first domain clock. A second circuit in a second clock domain is configured for operation with the second domain clock, and includes a second free-running counter with a pre-defined second selected roll-over count, to generate a second free-running count (N2(k)) based on the second domain clock.

公开(公告)号：US10187071B2

公开(公告)日：2019-01-22

申请号：US15387636

申请日：2016-12-21

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Himanshu Arora ,  Siraj Akhtar ,  Lu Sun ,  Hamid Safiri ,  Wenjing Lu ,  Nikolaus Klemmer

IPC: H03L7/099 ,  H03L7/10 ,  H03L1/02

Abstract: A PLL including a VCO with a variable capacitance (such as an LC VCO) including a switched capacitor bank and a varactor, the PLL providing lock range extension over temperature using dynamic capacitor bank switching to dynamically adjust varactor set point based on junction temperature. The varactor is responsive to the Vctrl control voltage to adjust a capacitance of the variable capacitance to control the phase of the PLL signal. Compensation circuitry dynamically adjusts varactor set point by dynamically switching the capacitor bank based in a junction temperature associated with the PLL circuitry, thereby extending PLL lock range over temperature.

公开(公告)号：US20170264302A1

公开(公告)日：2017-09-14

申请号：US15387636

申请日：2016-12-21

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Himanshu Arora ,  Siraj Akhtar ,  Lu Sun ,  Hamid Safiri ,  Wenjing Lu ,  Nikolaus Klemmer

IPC: H03L1/02 ,  H03L7/10

CPC classification number: H03L7/103 ,  H03L1/021 ,  H03L1/026 ,  H03L7/099 ,  H03L7/10 ,  H03L2207/06

Abstract: A multi-ladder DAC includes first and second resistor ladders, with a switch-interconnect. The switch-interconnect includes a second set of switches connected between each node of the first ladder and the top and bottom tap points of the second ladder. All other second ladder tap points are part of a loop tied to the nodes above and below each resistor through a second set of switches. Because no current flows through the switches that tie the top and bottom second-ladder tap points to the nodes of the first ladder, avoiding IRswitch error, thereby improving DNL.

公开(公告)号：US10218338B1

公开(公告)日：2019-02-26

申请号：US15782200

申请日：2017-10-12

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Nikolaus Klemmer ,  Chan Fernando ,  Jaimin Mehta ,  Srinadh Madhavapeddi ,  Hamid Safiri ,  Atul Kumar Jain

IPC: H03K3/84 ,  H03K5/1252 ,  H03K17/16

Abstract: Aperiodic clock generation with clock spur suppression is based on cascaded randomizers, such as for mixed signal devices. A clock generator circuit includes an input node to receive the input periodic clock signal having an input-clock frequency. A first randomizer circuit coupled to receive the input clock signal from the input node, to perform signal randomization to suppress spurious signal content associated with (a) the input clock signal, and (b) the first randomizer circuit, and to generate an intermediate clock signal. A second concatenated randomizer circuit is coupled to receive the intermediate clock signal, to perform signal randomization to suppress spurious signal content associated with (a) the intermediated clock signal, and (b) the second randomizer circuit, and to generate an aperiodic output clock signal having a pre-defined average output-clock frequency that is less than the input-clock frequency. Example randomizers are a delta-sigma divider and a pulse swallower (in any order).

公开(公告)号：US20160050035A1

公开(公告)日：2016-02-18

申请号：US14824062

申请日：2015-08-11

Applicant: Texas Instruments Incorporated

Inventor： Hunsoo Choo ,  Hamid Safiri ,  Nikolaus Klemmer

IPC: H04B17/21 ,  H04B17/318 ,  H04B17/23

CPC classification number: H04B17/21 ,  H04B17/23 ,  H04B17/318

Abstract: A signal profiler generates and monitors a signal profile corresponding to signal power (absolute or relative) per frequency band. The signal profiler includes a signal profile generator and a signal profile monitor. The signal profile generator processes a received signal in pre-defined frequency bands, and captures frequency-band signal power information into frequency bins, this frequency-binned signal power information constituting a signal profile. The signal profile monitor monitors the signal profile, including variations in the signal profile based on pre-defined criteria, and output corresponding profile-variation information (such as flags or interrupt requests). The signal profile generator is an FFT engine. The signal profile monitor is an FSM (finite state machine). An example application is use in a direct conversion wireless receiver to monitor relative image channel power as a signal profile variation that can be used to invoke QMC compensation/configuration.

Abstract translation: 信号剖析器产生并监视与每个频带的信号功率（绝对或相对）相对应的信号轮廓。 信号轮廓仪包括信号轮廓发生器和信号轮廓监视器。 信号分布发生器处理预定义频带中的接收信号，并将频带信号功率信息捕获到频率仓中，该频率合成信号功率信息构成信号分布。 信号配置文件监视器监视信号配置文件，包括基于预定义标准的信号配置文件的变化，并输出相应的配置文件变化信息（如标志或中断请求）。 信号分布生成器是FFT引擎。 信号轮廓监视器是FSM（有限状态机）。 示例应用在直接转换无线接收机中用于监视相对图像信道功率，作为可用于调用QMC补偿/配置的信号轮廓变化。