-
公开(公告)号：US20200266814A1
公开(公告)日：2020-08-20
申请号：US16867392
申请日：2020-05-05
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Amneh Mohammad Akour , Nikolaus Klemmer
IPC: H03K17/22
Abstract: A power-on-reset (POR) circuit for CMOS logic is operable to transition between a POR_active state and a POR_inactive state and can include: (a) VDD/VT threshold circuitry to provide a Vtp_threshold voltage based on input Vdd and PMOS Vtp, and a Vtn_threshold voltage based on input Vdd and NMOS Vtn; (b) POR transition detect circuitry to provide a POR_transition signal (active/inactive) based on a function(Vtp,Vtn), which is a function of Vtp_threshold and Vtn_threshold; and (c) POR transition control circuitry to provide the POR_state signal (active/inactive) based on the POR_transition signal. For a POR out-of-reset transition, the POR transition detect circuitry to switch the POR_transition signal inactive based on the function (Vtp,Vtn) corresponding to the POR_inactive state, and the POR transition control circuitry, responsive to the POR_transition signal switching to inactive, to initiate a POR out-of-reset delay period, and to signal the POR_inactive state after the POR out-of-reset delay period.
-
公开(公告)号：US10033427B2
公开(公告)日：2018-07-24
申请号：US14737191
申请日：2015-06-11
Applicant: Texas Instruments Incorporated
Inventor： Hunsoo Choo , Nikolaus Klemmer , Jaiminkumar Mehta
Abstract: A system for reducing a local oscillator leakage component. The system includes a transmitter channel to transmit data modulated using a transmitter local oscillator frequency. A transmitted signal includes a transmitter local oscillator leakage component. The system also includes a receiver channel to receive the transmitted signal using a receiver local oscillator signal having a frequency offset from the transmitter local oscillator frequency. The received signal includes the transmitter local oscillator leakage component isolated from one or more receiver impairments. The system further includes a feedback loop from the receiver channel to the transmitter channel to identify a power of the isolated transmitter local oscillator leakage component and to generate a local oscillator leakage cancellation signal based on the identified power.
-
公开(公告)号：US20170195002A1
公开(公告)日：2017-07-06
申请号：US15466418
申请日：2017-03-22
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Charles Kasimer Sestok, IV , Hunsoo Choo , Nikolaus Klemmer , Xiaoxi Zhang
CPC classification number: H04B1/406 , H04B1/1027 , H04B1/403 , H04L7/0331
Abstract: A phase rotator corrects the IQ imbalance in a wireless transceiver. The phase rotator is a part of a compensation system that detects and separates reception impairment images from transmission impairment images. The disclosed phase rotator introduces a phase shift between the transmission channel and the reception channel without perturbing the phase mismatch and the gain mismatch in the reception path. The phase rotator includes a first local oscillation (LO) circuit that generates a first LO signal at a first carrier frequency and a second LO circuit that generates a second LO signal at a second carrier frequency that deviates from the first carrier frequency for a phase rotation period. The phase rotation period is sufficiently long such that the frequency deviation can introduce a prescribed phase shift between the first LO signal and the second LO signal.
-
公开(公告)号：US20170111039A1
公开(公告)日：2017-04-20
申请号：US15299458
申请日：2016-10-20
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Amneh Mohammad Akour , Nikolaus Klemmer
IPC: H03K17/22
CPC classification number: H03K17/223
Abstract: A power-on-reset (POR) circuit is suitable for use in an integrated circuit including at least one CMOS logic block that includes PMOS and NMOS transistors respectively characterized by threshold voltages Vtp and Vtn, the CMOS circuitry operable with a power supply voltage Vdd. The POR circuit is operable to transition between a POR_active state and a POR_inactive state, including outputting a corresponding POR_state signal. The POR circuit includes: (a) VDD/VT threshold circuitry coupled to receive the Vdd voltage as an input to the POR circuit, and to provide a Vtp_threshold voltage based on Vdd and Vtp, and a Vtn_threshold voltage based on Vdd and Vtn; (b) POR transition detect circuitry coupled to the VDD/VT threshold circuitry to provide a POR_transition signal based on a function(Vtp,Vtn), which is a function of Vtp_threshold and Vtn_threshold; and (c) POR transition control circuitry coupled to the POR transition detect circuitry to provide the POW_state signal based on the POR_transition signal. For a POR out-of-reset transition of the POR_state signal from POR_active to POR_inactive, the POR transition detect circuitry is operable to switch the POR_transition signal from active to inactive based on the function (Vtp,Vtn) corresponding to the POR_inactive state, and the POR transition control circuitry is operable, in response to the POR_transition signal switching to inactive, to initiate a POR out-of-reset delay period, and to generate the POR_inactive signal after the POR out-of-reset delay period.
-
公开(公告)号：US09614510B2
公开(公告)日：2017-04-04
申请号：US15068231
申请日：2016-03-11
Applicant: Texas Instruments Incorporated
Inventor： Venkatesh Srinivasan , Kun Shi , Victoria Wang , Nikolaus Klemmer
CPC classification number: H03M3/38 , H03K5/159 , H03M1/001 , H03M1/164 , H03M3/37 , H03M3/386 , H03M3/464
Abstract: System and methods for input path matching in pipelined continuous-time Analog-to Digital Converters (ADCs), including pipelined Continuous-Time Delta Sigma Modulator (CTDSM) based ADCs, includes an input delay circuit disposed in a continuous-time input path from an input of an analog input signal to a first summing circuit of the continuous-time ADC. At least one digital delay line is disposed between an output of an earlier stage sub-ADC (of a plurality of pipelined sub-ADCs) and a sub-digital-to-analog converter (DAC) that is coupled to the first summing circuit, and between the earlier stage sub-ADC and a digital noise cancellation filter. The digital delay line(s) is configured to enable calibration of delay of output of the earlier stage sub-ADC provided to the sub-DAC and the digital noise cancellation filter in accordance with process variations of the input delay match circuit to minimize residue output at first summing circuit.
-
Patent Agency Ranking
公开(公告)号：US20170093279A1
公开(公告)日：2017-03-30
申请号：US14871140
申请日：2015-09-30
Applicant: Texas Instruments Incorporated
Inventor： Rahmi Hezar , Nikolaus Klemmer
Abstract: Noise-shaped frequency hopping power converters are disclosed. An example noise-shaped frequency hopping power converter comprises a shaped number generator having a first output to output a noise-shaped selection signal and a power converter having a first input to receive an input voltage signal, a second input to receive a switching signal that is based on the noise-shaped selection signal, and a second output to output an output voltage signal based on the switching signal.
-
公开(公告)号：US20160043697A1
公开(公告)日：2016-02-11
申请号：US14815619
申请日：2015-07-31
Applicant: Texas Instruments Incorporated
Inventor： Satish V. Uppathil , Nikolaus Klemmer , Fikret Dulger
CPC classification number: H03F1/223 , H03F3/195 , H03F3/45179 , H03F3/45242 , H03F2200/72 , H03F2200/75 , H03F2203/45024 , H03F2203/45306 , H03F2203/45392 , H03F2203/45481 , H03F2203/45631 , H04L27/3809
Abstract: A front-end receiver includes an amplifier that has a steady gain over a wide frequency range. The disclosed amplifier adopts an architecture in which a common-source (CS) circuit stacks against a common-gate (CG) circuit. The CG circuit provides the input impedance matching while the CS circuit boosts the amplification gain. As a result, the disclosed amplifier allows the front-end receiver to break free from a tradeoff between input impedance matching and gain boosting. Moreover, the disclosed amplifier achieves power saving and noise reduction by having the CS circuit to share the same bias current with the CG circuit.
Abstract translation: 前端接收机包括在宽频率范围内具有稳定增益的放大器。 所公开的放大器采用其中公共源（CS）电路堆叠到公共门（CG）电路的架构。 当CS电路提高放大增益时，CG电路提供输入阻抗匹配。 结果，所公开的放大器允许前端接收器摆脱输入阻抗匹配和增益提升之间的折中。 此外，所公开的放大器通过使CS电路与CG电路共享相同的偏置电流而实现功率节省和噪声降低。
-
8.发明授权公开(公告)号：US10778482B2
公开(公告)日：2020-09-15
申请号：US16515248
申请日：2019-07-18
Applicant: Texas Instruments Incorporated
Inventor： Nikolaus Klemmer , Amneh Mohammed Akour , Abhijit Anant Patki , Timothy Patrick Pauletti , Tarkesh Pande
Abstract: An integrated circuit includes a bit slicing circuit with a processing circuit. The processing circuit receives discrete frequency power estimates based on an S-FSK waveform received by an S-FSK receiver associated with the bit slicing circuit. The discrete frequency power estimates are representative of digital logic levels in a series of data frames modulated using S-FSK to form the S-FSK waveform. Each data frame including at least one word. Each word includes bit periods. The processing circuit receives SNR parameters that represent a dynamic SNR for the respective discrete frequency power estimates in relation to the series of data frames. The processing circuit selects a bit slicing technique from a set of available bit slicing techniques to generate data bit values for bit periods of the discrete frequency power estimates based on the SNR parameters. A method for performing bit slicing in an S-FSK receiver is also disclosed.
-
公开(公告)号：US20180219480A1
公开(公告)日：2018-08-02
申请号：US15422183
申请日：2017-02-01
Applicant: Texas Instruments Incorporated
Inventor： Rahmi Hezar , Nikolaus Klemmer
Abstract: Methods and apparatus for reducing electromagnetic interference in a power converter using phase hopping in conjunction with pulse width modulation are disclosed. An example power converter includes an input voltage to, when a control switching device receives a first voltage, increase an output voltage; and when the control switching device receives a second voltage, decrease the output voltage. The example power converter further includes a phase hopping generator to generate a phase varying signal corresponding to two or more phases, the phase varying signal corresponding to a reference voltage; and output the phase varying signal to control the control switching device.
-
公开(公告)号：US09641317B2
公开(公告)日：2017-05-02
申请号：US14814197
申请日：2015-07-30
Applicant: Texas Instruments Incorporated
Inventor： Charles Kasimer Sestok, IV , Hunsoo Choo , Nikolaus Klemmer , Xiaoxi Zhang
CPC classification number: H04B1/406 , H04B1/1027 , H04B1/403 , H04L7/0331
Abstract: A phase rotator corrects the IQ imbalance in a wireless transceiver. The phase rotator is a part of a compensation system that detects and separates reception impairment images from transmission impairment images. The disclosed phase rotator introduces a phase shift between the transmission channel and the reception channel without perturbing the phase mismatch and the gain mismatch in the reception path. The phase rotator includes a first local oscillation (LO) circuit that generates a first LO signal at a first carrier frequency and a second LO circuit that generates a second LO signal at a second carrier frequency that deviates from the first carrier frequency for a phase rotation period. The phase rotation period is sufficiently long such that the frequency deviation can introduce a prescribed phase shift between the first LO signal and the second LO signal.
-
-
-
-
-
-
-
-
-
Search Results
41
records
(took 0.02 seconds)
