Method for suppressing gate oxide tunnel current in non-volatile memory to reduce disturbs

    公开(公告)号:US10535409B2

    公开(公告)日:2020-01-14

    申请号:US15394095

    申请日:2016-12-29

    Abstract: A disturb management technique for a non-volatile memory including first and second memory cells includes programming the first memory cell by applying a first voltage to a first word line coupled to the first memory cell and a second voltage to a terminal, such as a source terminal, shared by the first memory cell and the second memory cell. A non-zero third voltage having the same sign as the second voltage is applied to a second word line coupled to the second memory cell. The applied non-zero third voltage reduces a tunnel current across a gate oxide that insulates the second word line from a substrate of the second memory cell. This results in the second memory cell having a lower likelihood of being disturbed when programming the first memory cell.

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