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1.
公开(公告)号:US10535409B2
公开(公告)日:2020-01-14
申请号:US15394095
申请日:2016-12-29
Applicant: Texas Instruments Incorporated
Inventor: Stephen K. Heinrich-Barna , Clyde F. Dunn , Aswin N. Mehta , John H. Macpeak
Abstract: A disturb management technique for a non-volatile memory including first and second memory cells includes programming the first memory cell by applying a first voltage to a first word line coupled to the first memory cell and a second voltage to a terminal, such as a source terminal, shared by the first memory cell and the second memory cell. A non-zero third voltage having the same sign as the second voltage is applied to a second word line coupled to the second memory cell. The applied non-zero third voltage reduces a tunnel current across a gate oxide that insulates the second word line from a substrate of the second memory cell. This results in the second memory cell having a lower likelihood of being disturbed when programming the first memory cell.
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公开(公告)号:US10446563B1
公开(公告)日:2019-10-15
申请号:US15945552
申请日:2018-04-04
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor: Xiang-Zheng Bo , John H. Macpeak , Douglas T. Grider
IPC: H01L21/00 , H01L27/11521 , H01L29/788 , H01L29/06 , H01L29/49 , H01L29/10 , H01L21/66 , H01L21/311 , H01L21/762 , H01L21/768 , H01L21/28 , H01L29/66 , H01L29/423 , H01L27/02 , H01L21/265 , G01N21/95 , G03F7/20
Abstract: In accordance with some examples, a system comprises a substrate layer having an outer surface. The system also comprises a plurality of trenches extending from the outer surface into the substrate layer. The system then comprises a plurality of active regions with each active region positioned between a different pair of consecutive trenches of the plurality of trenches. The system also comprises a dielectric layer disposed in each of the plurality of trenches and on each of the plurality of active regions. The system then comprises a floating gate layer disposed on the dielectric layer and extending at least partially into each of the plurality of trenches.
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