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公开(公告)号：US09019670B2
公开(公告)日：2015-04-28
申请号：US13751375
申请日：2013-01-28
CPC分类号： H02H3/20 , H01L27/0274 , H02H9/046
摘要： A structure is designed with an external terminal (100) and a reference terminal (102). A first transistor (106) is formed on a substrate. The first transistor has a current path coupled between the external terminal and the reference terminal. A second transistor (118) has a current path coupled between the external terminal and the substrate. A third transistor (120) has a current path coupled between the substrate and the reference terminal.
摘要翻译： 结构设计有外部端子（100）和参考端子（102）。 第一晶体管（106）形成在衬底上。 第一晶体管具有耦合在外部端子和参考端子之间的电流路径。 第二晶体管（118）具有耦合在外部端子和衬底之间的电流通路。 第三晶体管（120）具有耦合在衬底和参考端子之间的电流通路。
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公开(公告)号：US20140210053A1
公开(公告)日：2014-07-31
申请号：US13751381
申请日：2013-01-28
发明人： ROBERT STEINHOFF , Jonathan Brodsky
IPC分类号： H01L23/552 , H01L27/04
CPC分类号： H01L23/552 , H01L27/0207 , H01L27/0266 , H01L2924/0002 , H01L2924/00
摘要： A structure is designed with an external terminal (100) and a reference terminal (102). A first transistor (106) is formed on a substrate. The first transistor has a current path coupled between the external terminal and the reference terminal. A second transistor (118) has a current path coupled between the external terminal and the substrate. A third transistor (120) has a current path coupled between the substrate and the reference terminal.
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公开(公告)号：US20150103451A1
公开(公告)日：2015-04-16
申请号：US14514066
申请日：2014-10-14
发明人： Timothy Patrick Pauletti , Sameer Pendharkar , Wayne Tien-Feng Chen , Jonathan Brodsky , Robert Steinhoff
IPC分类号： H01L27/02
CPC分类号： H01L27/0262 , H01L29/7436 , H01L29/749 , H01L29/87 , H01L2924/0002 , H01L2924/00
摘要： An electrostatic discharge (ESD) device for protecting an input/output terminal of a circuit, the device comprising a first transistor with an integrated silicon-controlled rectifier (SCR) coupled between the input/output (I/O) terminal of the circuit and a node and a second transistor with an integrated silicon-controlled rectifier coupled between the node and a negative terminal of a supply voltage, wherein the silicon-controlled rectifier of the first transistor triggers in response to a negative ESD voltage and the silicon-controlled rectifier of the second transistor triggers in response to a positive ESD voltage.
摘要翻译： 一种用于保护电路的输入/输出端子的静电放电（ESD）装置，该装置包括：第一晶体管，其具有耦合在电路的输入/输出（I / O）端子之间的集成硅控整流器（SCR） 节点和第二晶体管，其具有耦合在所述节点和电源电压的负端子之间的集成硅控整流器，其中所述第一晶体管的所述硅控整流器响应于ESD ESD电压而触发，并且所述可硅可控整流器 的第二晶体管响应于正的ESD电压而触发。
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公开(公告)号：US09812439B2
公开(公告)日：2017-11-07
申请号：US14514066
申请日：2014-10-14
发明人： Timothy Patrick Pauletti , Sameer Pendharkar , Wayne Tien-Feng Chen , Jonathan Brodsky , Robert Steinhoff
IPC分类号： H02H9/04 , H01L27/02 , H01L29/74 , H01L29/87 , H01L29/749
CPC分类号： H01L27/0262 , H01L29/7436 , H01L29/749 , H01L29/87 , H01L2924/0002 , H01L2924/00
摘要： An electrostatic discharge (ESD) device for protecting an input/output terminal of a circuit, the device comprising a first transistor with an integrated silicon-controlled rectifier (SCR) coupled between the input/output (I/O) terminal of the circuit and a node and a second transistor with an integrated silicon-controlled rectifier coupled between the node and a negative terminal of a supply voltage, wherein the silicon-controlled rectifier of the first transistor triggers in response to a negative ESD voltage and the silicon-controlled rectifier of the second transistor triggers in response to a positive ESD voltage.
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公开(公告)号：US08916934B2
公开(公告)日：2014-12-23
申请号：US13751381
申请日：2013-01-28
IPC分类号： H01L23/62
CPC分类号： H01L23/552 , H01L27/0207 , H01L27/0266 , H01L2924/0002 , H01L2924/00
摘要： A structure is designed with an external terminal (100) and a reference terminal (102). A first transistor (106) is formed on a substrate. The first transistor has a current path coupled between the external terminal and the reference terminal. A second transistor (118) has a current path coupled between the external terminal and the substrate. A third transistor (120) has a current path coupled between the substrate and the reference terminal.
摘要翻译： 结构设计有外部端子（100）和参考端子（102）。 第一晶体管（106）形成在衬底上。 第一晶体管具有耦合在外部端子和参考端子之间的电流路径。 第二晶体管（118）具有耦合在外部端子和衬底之间的电流通路。 第三晶体管（120）具有耦合在衬底和参考端子之间的电流通路。
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公开(公告)号：US20140211347A1
公开(公告)日：2014-07-31
申请号：US13751375
申请日：2013-01-28
IPC分类号： H02H3/20 , H01L21/8228
CPC分类号： H02H3/20 , H01L27/0274 , H02H9/046
摘要： A structure is designed with an external terminal (100) and a reference terminal (102). A first transistor (106) is formed on a substrate. The first transistor has a current path coupled between the external terminal and the reference terminal. A second transistor (118) has a current path coupled between the external terminal and the substrate. A third transistor (120) has a current path coupled between the substrate and the reference terminal.
摘要翻译： 结构设计有外部端子（100）和参考端子（102）。 第一晶体管（106）形成在衬底上。 第一晶体管具有耦合在外部端子和参考端子之间的电流路径。 第二晶体管（118）具有耦合在外部端子和衬底之间的电流通路。 第三晶体管（120）具有耦合在衬底和参考端子之间的电流通路。
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