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    CIRCUIT AND ARCHITECTURE FOR A DEMODULATOR FOR A WIRELESS POWER TRANSFER SYSTEM AND METHOD THEREFOR
    3.
    发明申请
    CIRCUIT AND ARCHITECTURE FOR A DEMODULATOR FOR A WIRELESS POWER TRANSFER SYSTEM AND METHOD THEREFOR 有权
    一种用于无线电力传输系统的解调器的电路和结构及其方法

    公开(公告)号：US20150171935A1

    公开(公告)日：2015-06-18

    申请号：US14502048

    申请日：2014-09-30

    Applicant: Texas Instruments Incorporated

    Inventor： Ashish Khandelwal ,  Joseph M. Khayat ,  Yipeng Su ,  Robert A. Neidorff ,  Bharath B. Kannan

    IPC: H04B5/00

    CPC classification number: H02J50/10 ,  H02J5/005 ,  H02J7/025 ,  H02J50/80 ,  H03K5/1532 ,  H03K5/1536 ,  H03K5/24 ,  H03K19/20 ,  H03K2005/00078 ,  H04B5/0031 ,  H04B5/0037 ,  H04B5/0093 ,  H04B5/02

    Abstract: A primary side wireless power transmitter inductively couplable to a secondary side wireless power receiver for supplying power to the wireless power receiver for receiving communications from the secondary side wireless power receiver through the inductive coupling comprises a primary side tank circuit receiving a signal on from the secondary side wireless power receiver. A phase delay or time delay circuit generates a fixed delay clock signal. A sample and hold circuit samples a tank circuit voltage utilizing the fixed phase or time delayed clock signal. A comparator is coupled to an output of the sample and hold circuit for extracting data or commands from the signal stream. A method of operating a primary side wireless transmitter inductively coupled to a secondary side wireless power receiver for supplying power to the wireless power receiver to power a load coupled to the receiver is also disclosed.

    Abstract translation: 电感耦合到次级侧无线电力接收器的初级侧无线电力发射机用于向无线电力接收器供电以通过电感耦合从次级侧无线电力接收器接收通信包括初级侧电路接收来自次级侧的信号 侧无线电源接收器。 相位延迟或时间延迟电路产生固定的延迟时钟信号。 采样和保持电路利用固定相位或时间延迟的时钟信号对储能电路电压进行采样。 比较器耦合到采样和保持电路的输出端，用于从信号流中提取数据或命令。 还公开了一种操作初级侧无线发射机的方法，所述初级侧无线发射机感应耦合到次级侧无线电力接收机，用于向无线电力接收机供电以为耦合到接收机的负载供电。

    CIRCUIT FOR CURRENT SENSING IN HIGH-VOLTAGE TRANSISTOR
    6.
    发明申请
    CIRCUIT FOR CURRENT SENSING IN HIGH-VOLTAGE TRANSISTOR 审中-公开
    电流传感器在高压晶体管中的电路

    公开(公告)号：US20150102841A1

    公开(公告)日：2015-04-16

    申请号：US14516947

    申请日：2014-10-17

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Joseph M. Khayat ,  Marie Denison

    IPC: H03K17/08

    CPC classification number: H03K17/08 ,  H03K2217/0027

    Abstract: An integrated circuit including a high-voltage n-channel MOS power transistor, a high-voltage n-channel MOS blocking transistor, a high-voltage n-channel MOS reference transistor, and a voltage comparator, configured to provide an overcurrent signal if drain current through the power transistor in the on state exceeds a predetermined value. The power transistor source node is grounded. The blocking transistor drain node is connected to the power transistor drain node. The blocking transistor source node is coupled to the comparator non-inverting input. The reference transistor drain node is fed by a current source and is connected to the comparator inverting input. The reference transistor gate node is coupled to a gate node of the power transistor. The comparator output provides the overcurrent signal. A process of operating the integrated circuit is disclosed.

    Abstract translation: 包括高电压n沟道MOS功率晶体管，高压n沟道MOS截止晶体管，高压n沟道MOS参考晶体管和电压比较器的集成电路，被配置为在漏极 通过处于导通状态的功率晶体管的电流超过预定值。 功率晶体管源节点接地。 阻塞晶体管漏极节点连接到功率晶体管漏极节点。 阻塞晶体管源节点耦合到比较器同相输入。 参考晶体管漏极节点由电流源馈送并连接到比较器反相输入。 参考晶体管栅极节点耦合到功率晶体管的栅极节点。 比较器输出提供过电流信号。 公开了一种操作该集成电路的过程。

    Slew-rate control for transistors
    7.
    发明授权
    Slew-rate control for transistors 有权

    公开(公告)号：US12132489B2

    公开(公告)日：2024-10-29

    申请号：US18157288

    申请日：2023-01-20

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Joseph M. Khayat

    IPC: H03K5/04 ,  H03K3/012 ,  H03K5/08 ,  H03K17/687

    CPC classification number: H03K5/04 ,  H03K3/012 ,  H03K5/08 ,  H03K17/6871

    Abstract: A circuit includes an avalanche diode having an anode and a cathode. The circuit also includes a buffer stage having a buffer input, a power input and a buffer output, in which the buffer input is coupled to the anode, and the cathode is coupled to the power input. The circuit includes a transistor coupled between the power input and a clamp output. The transistor has a control input coupled to the buffer output, and a loop circuit is coupled between the buffer output and the buffer input. A capacitor is coupled between the buffer input and an output terminal.

    Circuit and architecture for a demodulator for a wireless power transfer system and method therefor
    8.
    发明授权
    Circuit and architecture for a demodulator for a wireless power transfer system and method therefor 有权
    一种用于无线电力传输系统的解调器的电路和结构及其方法

    公开(公告)号：US09362755B2

    公开(公告)日：2016-06-07

    申请号：US14502048

    申请日：2014-09-30

    Applicant: Texas Instruments Incorporated

    Inventor： Ashish Khandelwal ,  Joseph M. Khayat ,  Yipeng Su ,  Robert A. Neidorff ,  Bharath B. Kannan

    IPC: H04B5/00 ,  H02J5/00 ,  H03K19/20 ,  H04B5/02 ,  H02J7/02

    CPC classification number: H02J50/10 ,  H02J5/005 ,  H02J7/025 ,  H02J50/80 ,  H03K5/1532 ,  H03K5/1536 ,  H03K5/24 ,  H03K19/20 ,  H03K2005/00078 ,  H04B5/0031 ,  H04B5/0037 ,  H04B5/0093 ,  H04B5/02

    Abstract: A primary side wireless power transmitter inductively couplable to a secondary side wireless power receiver for supplying power to the wireless power receiver for receiving communications from the secondary side wireless power receiver through the inductive coupling comprises a primary side tank circuit receiving a signal on from the secondary side wireless power receiver. A phase delay or time delay circuit generates a fixed delay clock signal. A sample and hold circuit samples a tank circuit voltage utilizing the fixed phase or time delayed clock signal. A comparator is coupled to an output of the sample and hold circuit for extracting data or commands from the signal stream. A method of operating a primary side wireless transmitter inductively coupled to a secondary side wireless power receiver for supplying power to the wireless power receiver to power a load coupled to the receiver is also disclosed.

    Abstract translation: 电感耦合到次级侧无线电力接收器的初级侧无线电力发射器，用于向无线电力接收器供电以通过电感耦合从次级侧无线电力接收器接收通信，包括初级侧电路接收来自次级侧的信号 侧无线电源接收器。 相位延迟或时间延迟电路产生固定的延迟时钟信号。 采样和保持电路利用固定相位或时间延迟的时钟信号对储能电路电压进行采样。 比较器耦合到采样和保持电路的输出端，用于从信号流中提取数据或命令。 还公开了一种操作初级侧无线发射机的方法，所述初级侧无线发射机感应耦合到次级侧无线电力接收机，用于向无线电力接收机供电以为耦合到接收机的负载供电。

    Circuit for current sensing in high-voltage transistor
    9.
    发明授权
    Circuit for current sensing in high-voltage transistor 有权
    高压晶体管电流检测电路

    公开(公告)号：US09294082B2

    公开(公告)日：2016-03-22

    申请号：US14516947

    申请日：2014-10-17

    Applicant: Texas Instruments Incorporated

    Inventor： Joseph M. Khayat ,  Marie Denison

    IPC: H03K3/00 ,  H03K17/08

    CPC classification number: H03K17/08 ,  H03K2217/0027

    Abstract: An integrated circuit including a high-voltage n-channel MOS power transistor, a high-voltage n-channel MOS blocking transistor, a high-voltage n-channel MOS reference transistor, and a voltage comparator, configured to provide an overcurrent signal if drain current through the power transistor in the on state exceeds a predetermined value. The power transistor source node is grounded. The blocking transistor drain node is connected to the power transistor drain node. The blocking transistor source node is coupled to the comparator non-inverting input. The reference transistor drain node is fed by a current source and is connected to the comparator inverting input. The reference transistor gate node is coupled to a gate node of the power transistor. The comparator output provides the overcurrent signal. A process of operating the integrated circuit is disclosed.

    Abstract translation: 包括高电压n沟道MOS功率晶体管，高压n沟道MOS截止晶体管，高压n沟道MOS参考晶体管和电压比较器的集成电路，被配置为在漏极 通过处于导通状态的功率晶体管的电流超过预定值。 功率晶体管源节点接地。 阻塞晶体管漏极节点连接到功率晶体管漏极节点。 阻塞晶体管源节点耦合到比较器同相输入。 参考晶体管漏极节点由电流源馈送并连接到比较器反相输入。 参考晶体管栅极节点耦合到功率晶体管的栅极节点。 比较器输出提供过电流信号。 公开了一种操作该集成电路的过程。

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