公开(公告)号：US10305507B1

公开(公告)日：2019-05-28

申请号：US15982670

申请日：2018-05-17

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jerry Lee Doorenbos ,  Keith Eric Sanborn ,  Mina Raymond Naguib Nashed ,  Srikanth Vellore Avadhanam Ramamurthy ,  Dwight David Griffin

IPC: H03M3/00

Abstract: A first-order sigma-delta analog-to-digital converter includes an input terminal, an integrator circuit, a comparator, and control circuitry. The input terminal is configured to receive a unipolar input signal to be digitized. The integrator circuit is coupled to the input terminal. The comparator is coupled to an output of the integrator circuit. The control circuitry is coupled to the integrator circuit and the comparator. The control circuitry is configured to equalize time that an output signal generated by the integrator circuit is greater than zero and time that the output signal generated by the integrator circuit is less than zero during digitization of the unipolar input signal.

公开(公告)号：US20210343694A1

公开(公告)日：2021-11-04

申请号：US17376747

申请日：2021-07-15

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Steve Edward Harrell ,  Keith Eric Sanborn ,  Wai Lee ,  Erika Lynn Mazotti

IPC: H01L27/00 ,  H01L23/525 ,  H01L27/08

Abstract: An electronic device, e.g. a trimmable resistor, includes a plurality of fused resistors, each fused resistor including one or more doped resistive regions formed in a semiconductor substrate. The doped resistive regions may be thermistors. Each fused resistor further includes a corresponding one of a plurality of fusible links. A first terminal of each of the fused resistors is connected to a first terminal of the corresponding fusible link. First and second interconnection buses are located over the substrate, with the first interconnection bus connecting to a second terminal of each of the fused resistors, and the second interconnection bus connecting to a second terminal of each of the fusible links. The plurality of fused resistors have resistance values that form an exponential progression.

公开(公告)号：US20220382304A1

公开(公告)日：2022-12-01

申请号：US17395680

申请日：2021-08-06

Applicant: Texas Instruments Incorporated

Inventor： Ryan Wade Selby ,  Shobha Subramanian ,  Hussain Attarwala ,  Keith Eric Sanborn ,  Mihail Gurevitch

IPC: G05D23/20 ,  H05B3/00 ,  H05B1/02 ,  G05D22/02

Abstract: Various examples are provided of low power, rapid response on-device heaters and methods of calibrating the device within a linear operating region, which is reached and maintained through control of the on-device heater. A system to be calibrated includes a sensor to measure the temperature and relative humidity of the system, a heater coupled to the sensor, a heater controller coupled to the heater to control the heater to heat the system, and a processor coupled to the sensor and the heater controller. The processor controls the heater based on temperature measured by the sensor to perform a calibration process for the system including calculating a calibration factor, and to determine whether to abort the calibration process based on relative humidity measured by the sensor indicating that the system is outside the linear operating region.

公开(公告)号：US20200075573A1

公开(公告)日：2020-03-05

申请号：US16547615

申请日：2019-08-22

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Steve Edward Harrell ,  Keith Eric Sanborn ,  Wai Lee ,  Erika Lynn Mazotti

IPC: H01L27/00 ,  H01L23/525

Abstract: An electronic device, e.g. a trimmable resistor, includes a plurality of fused resistors, each fused resistor including one or more doped resistive regions formed in a semiconductor substrate. The doped resistive regions may be thermistors. Each fused resistor further includes a corresponding one of a plurality of fusible links. A first terminal of each of the fused resistors is connected to a first terminal of the corresponding fusible link. First and second interconnection buses are located over the substrate, with the first interconnection bus connecting to a second terminal of each of the fused resistors, and the second interconnection bus connecting to a second terminal of each of the fusible links. The plurality of fused resistors have resistance values that form an exponential progression.

公开(公告)号：US11101263B2

公开(公告)日：2021-08-24

申请号：US16547615

申请日：2019-08-22

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Steve Edward Harrell ,  Keith Eric Sanborn ,  Wai Lee ,  Erika Lynn Mazotti

IPC: H01L27/00 ,  H01L23/525 ,  H01L27/08 ,  H01L49/02

Abstract: An electronic device, e.g. a trimmable resistor, includes a plurality of fused resistors, each fused resistor including one or more doped resistive regions formed in a semiconductor substrate. The doped resistive regions may be thermistors. Each fused resistor further includes a corresponding one of a plurality of fusible links. A first terminal of each of the fused resistors is connected to a first terminal of the corresponding fusible link. First and second interconnection buses are located over the substrate, with the first interconnection bus connecting to a second terminal of each of the fused resistors, and the second interconnection bus connecting to a second terminal of each of the fusible links. The plurality of fused resistors have resistance values that form an exponential progression.

公开(公告)号：US10461771B2

公开(公告)日：2019-10-29

申请号：US16054877

申请日：2018-08-03

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jerry Lee Doorenbos ,  Keith Eric Sanborn ,  Srikanth Vellore Avadhanam Ramamurthy ,  Mina Raymond Naguib Nashed ,  Dwight David Griffin

IPC: H03M3/00

Abstract: In some examples, a sigma-delta analog-to-digital converter (ADC), comprises a first set of switches configured to receive a first voltage signal; a second set of switches coupled to the first set of switches at a first node and a second node, the second set of switches configured to receive a second voltage signal; an integrator including a first input sampling capacitor coupled to the first node and a second input sampling capacitor coupled to the second node, wherein the integrator configured to generate a first output signal. The sigma-delta ADC further comprises a comparator coupled to the integrator and configured to generate a second output signal based on the first output signal; and a controller unit having a first counter, a second counter, and a processor, the controller unit coupled to the first and second sets of switches, the integrator, and the comparator.