公开(公告)号：US11880333B2

公开(公告)日：2024-01-23

申请号：US17314313

申请日：2021-05-07

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jason A. T. Jones ,  Sriramakrishnan Govindarajan ,  Mihir Narendra Mody ,  Kishon Vijay Abraham Israel Vijayponraj ,  Bradley Douglas Cobb ,  Sanand Prasad ,  Gregory Raymond Shurtz ,  Martin Jeffrey Ambrose ,  Jayant Thakur

IPC: G06F15/78 ,  G06F13/10

CPC classification number: G06F15/7807 ,  G06F13/10 ,  G06F15/7864

Abstract: An integrated circuit. The integrated circuit comprises an interconnect communication bus and a plurality of peripheral component interconnect (PCI) multi-function endpoints (MFN-EPs) coupled to the interconnect communication bus, each PCI MFN-EP comprising a multiplexing device, a first address translation unit (ATU), and at least one PCI function circuit, each PCI function circuit comprising another ATU and a plurality of base address registers (BARs).

公开(公告)号：US09240189B2

公开(公告)日：2016-01-19

申请号：US14149981

申请日：2014-01-08

Applicant: Texas Instruments Incorporated

Inventor： Martin Jeffrey Ambrose ,  Lester Anderson Longley

IPC: G10L19/00

CPC classification number: G10L19/00

Abstract: A method and apparatus for processing encoded audio data that operates on batches of data having a predetermined time block size. An input/output memory buffer provides a delay from input to corresponding output of 2+x time blocks where x is a predetermined constant and 0

Abstract translation: 一种用于处理对具有预定时间块大小的批次的数据进行操作的编码音频数据的方法和装置。 输入/输出存储器缓冲器提供从输入到2 + x时间块的相应输出的延迟，其中x是预定常数且0

公开(公告)号：US20210263883A1

公开(公告)日：2021-08-26

申请号：US17314313

申请日：2021-05-07

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jason A.T. Jones ,  Sriramakrishnan Govindarajan ,  Mihir Narendra Mody ,  Kishon Vijay Abraham Israel Vijayponraj ,  Bradley Douglas Cobb ,  Sanand Prasad ,  Gregory Raymond Shurtz ,  Martin Jeffrey Ambrose ,  Jayant Thakur

IPC: G06F15/78 ,  G06F13/10

Abstract: An integrated circuit. The integrated circuit comprises an interconnect communication bus and a plurality of peripheral component interconnect (PCI) multi-function endpoints (MFN-EPs) coupled to the interconnect communication bus, each PCI MFN-EP comprising a multiplexing device, a first address translation unit (ATU), and at least one PCI function circuit, each PCI function circuit comprising another ATU and a plurality of base address registers (BARs).

公开(公告)号：US11030144B2

公开(公告)日：2021-06-08

申请号：US16221364

申请日：2018-12-14

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jason A. T. Jones ,  Sriramakrishnan Govindarajan ,  Mihir Narendra Mody ,  Kishon Vijay Abraham Israel Vijayponraj ,  Bradley Douglas Cobb ,  Sanand Prasad ,  Gregory Raymond Shurtz ,  Martin Jeffrey Ambrose ,  Jayant Thakur

IPC: G06F15/78 ,  G06F13/10

Abstract: An integrated circuit. The integrated circuit comprises an interconnect communication bus and a plurality of peripheral component interconnect (PCI) multi-function endpoints (MFN-EPs) coupled to the interconnect communication bus, each PCI MFN-EP comprising a multiplexing device, a first address translation unit (ATU), and at least one PCI function circuit, each PCI function circuit comprising another ATU and a plurality of base address registers (BARs).

公开(公告)号：US20140257823A1

公开(公告)日：2014-09-11

申请号：US14149981

申请日：2014-01-08

Applicant: Texas Instruments Incorporated

Inventor： Martin Jeffrey Ambrose ,  Lester Anderson Longley

IPC: G10L19/00

CPC classification number: G10L19/00

Abstract: A method and apparatus for processing encoded audio data that operates on batches of data having a predetermined time block size. An input/output memory buffer provides a delay from input to corresponding output of 2+x time blocks where x is a predetermined constant and 0

Abstract translation: 一种用于处理对具有预定时间块大小的批次的数据进行操作的编码音频数据的方法和装置。 输入/输出存储器缓冲器提供从输入到2 + x时间块的相应输出的延迟，其中x是预定常数且0