公开(公告)号：US20230412431A1

公开(公告)日：2023-12-21

申请号：US18241544

申请日：2023-09-01

Applicant: Texas Instruments Incorporated

Inventor： Sadia Arefin KHAN ,  Anant Shankar KAMATH ,  Martin STAEBLER ,  Vikas Kumar THAWANI

IPC: H04L25/02 ,  H02K11/33 ,  H03K19/0175 ,  H03K19/003 ,  H02P27/08

CPC classification number: H04L25/0266 ,  H02K11/33 ,  H03K19/017545 ,  H03K19/00323 ,  H03K19/017509 ,  H02P27/08

Abstract: A multi-channel digital isolator includes a digital isolator and an interlock circuit. The isolator includes a transmitter having a transmitter output, a receiver having a receiver input and a receiver output, an isolation barrier coupled between the transmitter output and the receiver input, and an output buffer having a buffer input and configured to output an isolated signal. The transmitter is configured to transmit an input signal across the isolation barrier. The interlock circuit has an interlock input coupled to the receiver output and an interlock output coupled to the buffer input. The interlock module is configured to prevent overlapping active states between the first isolated signal and a complementary isolated signal. In some implementations, the digital isolator also includes a dead-time insertion circuit.

公开(公告)号：US20190372566A1

公开(公告)日：2019-12-05

申请号：US16424862

申请日：2019-05-29

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Thomas Anton LEYRER ,  Martin STAEBLER ,  William Cronin WALLACE

IPC: H03K7/08 ,  H03K19/00 ,  G06F11/07

Abstract: An integrated communications subsystem (ICSS) includes a pulse-width modulator which drives a power stage, such as a motor. The pulse-width modulator is configured shut off the power stage when the pulse-width modulator receives a trip signal from a logic circuit of the ICSS. The logic circuit can easily be reprogrammed to send a trip signal only when certain error conditions are detected. Moreover, the ICSS contains one or more filters which can adjust the sensitivity of the logic circuit to error signals, enabling the ICSS to distinguish between true errors which require shutdown and glitches, which can be ignored during operation of the ICSS.

公开(公告)号：US20220021562A1

公开(公告)日：2022-01-20

申请号：US17352663

申请日：2021-06-21

Applicant: Texas Instruments Incorporated

Inventor： Sadia Arefin KHAN ,  Anant Shankar KAMATH ,  Martin STAEBLER ,  Vikas Kumar THAWANI

IPC: H04L25/02 ,  H02K11/33 ,  H02P27/08 ,  H03K19/003 ,  H03K19/0175

Abstract: A multi-channel digital isolator includes a digital isolator and an interlock circuit. The isolator includes a transmitter having a transmitter output, a receiver having a receiver input and a receiver output, an isolation barrier coupled between the transmitter output and the receiver input, and an output buffer having a buffer input and configured to output an isolated signal. The transmitter is configured to transmit an input signal across the isolation barrier. The interlock circuit has an interlock input coupled to the receiver output and an interlock output coupled to the buffer input. The interlock module is configured to prevent overlapping active states between the first isolated signal and a complementary isolated signal. In some implementations, the digital isolator also includes a dead-time insertion circuit.

公开(公告)号：US20210028777A1

公开(公告)日：2021-01-28

申请号：US17066660

申请日：2020-10-09

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Thomas Anton LEYRER ,  Martin STAEBLER ,  William Cronin WALLACE

IPC: H03K7/08 ,  H03K19/00 ,  H02P3/18 ,  G06F11/07

Abstract: An integrated communications subsystem (ICSS) includes a pulse-width modulator which drives a power stage, such as a motor. The pulse-width modulator is configured shut off the power stage when the pulse-width modulator receives a trip signal from a logic circuit of the ICSS. The logic circuit can easily be reprogrammed to send a trip signal only when certain error conditions are detected. Moreover, the ICSS contains one or more filters which can adjust the sensitivity of the logic circuit to error signals, enabling the ICSS to distinguish between true errors which require shutdown and glitches, which can be ignored during operation of the ICSS.

公开(公告)号：US20190372488A1

公开(公告)日：2019-12-05

申请号：US16544249

申请日：2019-08-19

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Martin STAEBLER ,  Ferdinand von MOLO

IPC: H02P6/16 ,  G01D18/00 ,  G01D5/244

Abstract: A sort buffer includes a phase sector determination circuit, a phase sector update circuit, and a phase sector completion circuit. The phase sector determination circuit is configured to determine a phase sector corresponding to a phase of a first sine and cosine sample pair received from an encoder or resolver. The phase sector update circuit is configured to determine whether a second sine and cosine sample pair corresponding to the phase sector is stored in a lookup table (LUT) and, in response to a determination that a second sine and cosine sample pair corresponding to the phase sector is not stored in the LUT, store the first sine and cosine sample pair in the LUT. The phase sector completion circuit is configured to determine whether the LUT has stored, for each of a plurality of phase sectors, a corresponding sine and cosine sample pair.