公开(公告)号：US10522663B2

公开(公告)日：2019-12-31

申请号：US15999542

申请日：2018-08-20

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Alexei Sadovnikov ,  Doug Weiser ,  Mattias Erik Dahlstrom ,  Joel Martin Halbert

IPC: H01L29/66 ,  H01L29/808 ,  H01L29/10 ,  H01L21/265 ,  H01L21/324 ,  H01L23/535 ,  H01L29/06

Abstract: A method of forming an electronic device includes forming first, second and third doped regions at a surface of a semiconductor substrate. A first buried layer is located within the semiconductor substrate below the first, second and third doped regions. Fourth and fifth doped regions are laterally spaced apart along the substrate and extend from the surface of the substrate to the first buried layer, the first, second and third doped regions being located between the fourth and fifth doped regions. A second buried layer is formed within the substrate and between the fourth and fifth doped regions such that a first portion of the semiconductor substrate is located between the first buried layer and the second buried layer, and a second portion of the semiconductor substrate is located between the first, second and third doped regions and the second buried layer.

公开(公告)号：US20190019884A1

公开(公告)日：2019-01-17

申请号：US15999542

申请日：2018-08-20

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Alexei Sadovnikov ,  Doug Weiser ,  Mattias Erik Dahlstrom ,  Joel Martin Halbert

IPC: H01L29/66 ,  H01L29/808 ,  H01L29/10 ,  H01L21/265 ,  H01L23/535 ,  H01L21/324 ,  H01L29/06

CPC classification number: H01L29/66916 ,  H01L21/265 ,  H01L21/324 ,  H01L23/535 ,  H01L29/0692 ,  H01L29/1058 ,  H01L29/1066 ,  H01L29/808 ,  H01L29/8086

Abstract: A method of forming an electronic device includes forming first, second and third doped regions at a surface of a semiconductor substrate. A first buried layer is located within the semiconductor substrate below the first, second and third doped regions. Fourth and fifth doped regions are laterally spaced apart along the substrate and extend from the surface of the substrate to the first buried layer, the first, second and third doped regions being located between the fourth and fifth doped regions. A second buried layer is formed within the substrate and between the fourth and fifth doped regions such that a first portion of the semiconductor substrate is located between the first buried layer and the second buried layer, and a second portion of the semiconductor substrate is located between the first, second and third doped regions and the second buried layer.

公开(公告)号：US10079294B2

公开(公告)日：2018-09-18

申请号：US15195287

申请日：2016-06-28

Applicant: Texas Instruments Incorporated

Inventor： Alexei Sadovnikov ,  Doug Weiser ,  Mattias Erik Dahlstrom ,  Joel Martin Halbert

IPC: H01L29/66 ,  H01L21/265 ,  H01L21/324 ,  H01L23/535 ,  H01L29/808

CPC classification number: H01L29/66916 ,  H01L21/265 ,  H01L21/324 ,  H01L23/535 ,  H01L29/0692 ,  H01L29/1058 ,  H01L29/1066 ,  H01L29/808 ,  H01L29/8086

Abstract: A semiconductor device contains a JFET with a channel layer having a first conductivity type in a substrate. The JFET has a back gate having a second, opposite, conductivity type below the channel. The back gate is laterally aligned with the channel layer. The semiconductor device is formed by forming a channel mask over the substrate of the semiconductor device which exposes an area for the channel dopants. The channel dopants are implanted into the substrate in the area exposed by the channel mask while the channel mask is in place. The back gate dopants are implanted into the substrate while the channel mask is in place, so that the implanted channel dopants are laterally aligned with the implanted channel dopants.

公开(公告)号：US20170373171A1

公开(公告)日：2017-12-28

申请号：US15195287

申请日：2016-06-28

Applicant: Texas Instruments Incorporated

Inventor： Alexei Sadovnikov ,  Doug Weiser ,  Mattias Erik Dahlstrom ,  Joel Martin Halbert

IPC: H01L29/66 ,  H01L23/535 ,  H01L21/324 ,  H01L29/808 ,  H01L21/265

CPC classification number: H01L29/66916 ,  H01L21/265 ,  H01L21/324 ,  H01L23/535 ,  H01L29/0692 ,  H01L29/1058 ,  H01L29/1066 ,  H01L29/808 ,  H01L29/8086

Abstract: A semiconductor device contains a JFET with a channel layer having a first conductivity type in a substrate. The JFET has a back gate having a second, opposite, conductivity type below the channel. The back gate is laterally aligned with the channel layer. The semiconductor device is formed by forming a channel mask over the substrate of the semiconductor device which exposes an area for the channel dopants. The channel dopants are implanted into the substrate in the area exposed by the channel mask while the channel mask is in place. The back gate dopants are implanted into the substrate while the channel mask is in place, so that the implanted channel dopants are laterally aligned with the implanted channel dopants.