公开(公告)号：US08839063B2

公开(公告)日：2014-09-16

申请号：US13749623

申请日：2013-01-24

Applicant: Texas Instruments Incorporated

Inventor： Rubin Ajit Parekhji ,  Srivaths Ravi ,  Prakash Narayanan ,  Milan Shetty

IPC: G01R31/28 ,  G06F11/00

CPC classification number: G01R31/318544 ,  G01R31/318572

Abstract: A method of testing devices under test (DUTs) and testing system are disclosed. The method comprises generating at least one control signal associated with a test pattern structure received from a testing system. The method further comprises selecting M1 number of ports from M number of I/O ports in the DUT to receive scan input corresponding to the test pattern structure based on the control signal, selecting M2 number of ports from the M number of I/O ports to provide scan output based on the control signal, wherein each of M1 and M2 is a number selected from 0 to M, and wherein a sum of M1 and M2 is less than or equal to M. Thereafter, the method comprises performing a scan testing of the DUT based on the scan input provided to the M1 number of ports and receiving the scan output from the M2 number of ports.

Abstract translation: 公开了一种测试被测设备（DUT）和测试系统的方法。 该方法包括生成与从测试系统接收的测试图案结构相关联的至少一个控制信号。 该方法进一步包括从DUT中的M个I / O端口中选择M1个端口，以基于控制信号接收与测试模式结构相对应的扫描输入，从M个I / O端口中选择M2个端口 以提供基于控制信号的扫描输出，其中M1和M2中的每一个是从0到M中选择的数字，并且其中M1和M2的和小于或等于M.此后，该方法包括执行扫描测试 基于提供给M1端口的扫描输入并从M2端口接收扫描输出的DUT的DUT。

公开(公告)号：US20140208177A1

公开(公告)日：2014-07-24

申请号：US13749623

申请日：2013-01-24

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Rubin Ajit Parekhji ,  Srivaths Ravi ,  Prakash Narayanan ,  Milan Shetty

IPC: G01R31/3177

CPC classification number: G01R31/318544 ,  G01R31/318572

Abstract: A method of testing devices under test (DUTs) and testing system are disclosed. The method comprises generating at least one control signal associated with a test pattern structure received from a testing system. The method further comprises selecting M1 number of ports from M number of I/O ports in the DUT to receive scan input corresponding to the test pattern structure based on the control signal, selecting M2 number of ports from the M number of I/O ports to provide scan output based on the control signal, wherein each of M1 and M2 is a number selected from 0 to M, and wherein a sum of M1 and M2 is less than or equal to M. Thereafter, the method comprises performing a scan testing of the DUT based on the scan input provided to the M1 number of ports and receiving the scan output from the M2 number of ports.

Abstract translation: 公开了一种测试被测设备（DUT）和测试系统的方法。 该方法包括生成与从测试系统接收的测试图案结构相关联的至少一个控制信号。 该方法进一步包括从DUT中的M个I / O端口中选择M1个端口，以基于控制信号接收与测试模式结构相对应的扫描输入，从M个I / O端口中选择M2个端口 以提供基于控制信号的扫描输出，其中M1和M2中的每一个是从0到M中选择的数字，并且其中M1和M2的和小于或等于M.此后，该方法包括执行扫描测试 基于提供给M1端口的扫描输入并从M2端口接收扫描输出的DUT的DUT。

公开(公告)号：US09797948B2

公开(公告)日：2017-10-24

申请号：US14830899

申请日：2015-08-20

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Milan Shetty ,  Srinivasulu Alampally ,  Prasanth V

IPC: G01R31/28 ,  G01R31/3177 ,  G01R31/317 ,  G01R31/3185

CPC classification number: G01R31/3177 ,  G01R31/31727 ,  G01R31/31855

Abstract: A multi-die chip module (MCM) comprises a first die containing a first test controller and a second die containing a second test controller coupled to the first die via an interconnect. The first test controller is configured to place the first die in either a shift mode or a capture mode. The second controller is configured to place the second die in either the shift mode or the capture mode. After a scan shift operation, scan cells are initialized to predetermined values. During the capture operation one die remains in the shift mode and the other die enters the capture mode so that as test bits are shifted into registers associated with output pads on the die in the shift mode, the other die is in the capture mode and captures signals on input pads associated with that die, enabling scan based at-speed testing of the interconnect.

公开(公告)号：US20150355278A1

公开(公告)日：2015-12-10

申请号：US14830899

申请日：2015-08-20

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Milan Shetty ,  Srinivasulu Alampally ,  Prasanth V

IPC: G01R31/3177 ,  G01R31/317

CPC classification number: G01R31/3177 ,  G01R31/31727 ,  G01R31/31855

Abstract: A multi-die chip module (MCM) comprises a first die containing a first test controller and a second die containing a second test controller coupled to the first die via an interconnect. The first test controller is configured to place the first die in either a shift mode or a capture mode. The second controller is configured to place the second die in either the shift mode or the capture mode. After a scan shift operation, scan cells are initialized to predetermined values. During the capture operation one die remains in the shift mode and the other die enters the capture mode so that as test bits are shifted into registers associated with output pads on the die in the shift mode, the other die is in the capture mode and captures signals on input pads associated with that die, enabling scan based at-speed testing of the interconnect.

Abstract translation: 多芯片芯片模块（MCM）包括：第一模具，其包含第一测试控制器和第二模具，所述第二模具包含经由互连件耦合到所述第一裸片的第二测试控制器。 第一测试控制器被配置为将第一管芯置于移动模式或捕获模式中。 第二控制器被配置为将第二管芯置于移动模式或捕获模式中。 在扫描移位操作之后，扫描单元被初始化为预定值。 在捕捉操作期间，一个管芯保持在移位模式，另一个管芯进入捕获模式，使得随着测试位在移位模式下移入与管芯上的输出焊盘相关联的寄存器中，另一个管芯处于捕获模式并捕获 与该芯片相关的输入焊盘上的信号，使得能够进行基于扫描的互连的高速测试。