公开(公告)号：US20140208177A1

公开(公告)日：2014-07-24

申请号：US13749623

申请日：2013-01-24

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Rubin Ajit Parekhji ,  Srivaths Ravi ,  Prakash Narayanan ,  Milan Shetty

IPC: G01R31/3177

CPC classification number: G01R31/318544 ,  G01R31/318572

Abstract: A method of testing devices under test (DUTs) and testing system are disclosed. The method comprises generating at least one control signal associated with a test pattern structure received from a testing system. The method further comprises selecting M1 number of ports from M number of I/O ports in the DUT to receive scan input corresponding to the test pattern structure based on the control signal, selecting M2 number of ports from the M number of I/O ports to provide scan output based on the control signal, wherein each of M1 and M2 is a number selected from 0 to M, and wherein a sum of M1 and M2 is less than or equal to M. Thereafter, the method comprises performing a scan testing of the DUT based on the scan input provided to the M1 number of ports and receiving the scan output from the M2 number of ports.

Abstract translation: 公开了一种测试被测设备（DUT）和测试系统的方法。 该方法包括生成与从测试系统接收的测试图案结构相关联的至少一个控制信号。 该方法进一步包括从DUT中的M个I / O端口中选择M1个端口，以基于控制信号接收与测试模式结构相对应的扫描输入，从M个I / O端口中选择M2个端口 以提供基于控制信号的扫描输出，其中M1和M2中的每一个是从0到M中选择的数字，并且其中M1和M2的和小于或等于M.此后，该方法包括执行扫描测试 基于提供给M1端口的扫描输入并从M2端口接收扫描输出的DUT的DUT。

公开(公告)号：US20200379031A1

公开(公告)日：2020-12-03

申请号：US16901966

申请日：2020-06-15

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Rubin Ajit Parekhji ,  Mahesh M. Mehendale ,  Vinod Menezes ,  Vipul K. Singhal

IPC: G01R31/28 ,  G01R31/3185 ,  G01R1/04 ,  G01R1/067

Abstract: In a method of testing a semiconductor wafer, a probe tip contacts a pad in a scribe line space between facing sides of first and second dies. The probe tip is electrically coupled to an automated test equipment (ATE). The second die is spaced apart from the first die. The scribe line space includes an interconnect extending along at least an entire length of the facing sides of the first and second dies. The pad is electrically coupled through the interconnect to at least one of the first or second dies. With the ATE, circuitry is tested in at least one of the first or second dies. The pad is electrically coupled through the interconnect to the circuitry.

公开(公告)号：US10746797B1

公开(公告)日：2020-08-18

申请号：US16390090

申请日：2019-04-22

Applicant: Texas Instruments Incorporated

Inventor： Rubin Ajit Parekhji ,  Mudasir Shafat Kawoosa

IPC: G01R31/3177 ,  G06F11/263 ,  G01R31/317 ,  G01R31/3185

Abstract: A method of testing a device under test, the device under test comprising a scan chain having a number of storage elements. The method determines a representation of toggling events in a test sequence, where the test sequence is for testing the scan chain. The method also selectively times input of a bit sequence, corresponding to the test sequence, to a first storage element in the number of storage elements, and through the scan chain, in response to the determining step.

公开(公告)号：US20200057106A1

公开(公告)日：2020-02-20

申请号：US16538518

申请日：2019-08-12

Applicant: Texas Instruments Incorporated

Inventor： Lakshmanan Balasubramanian ,  Nadeem Husain Tehsildar ,  Rubin Ajit Parekhji ,  Suresh Mallala ,  Nitin Agarwal

IPC: G01R31/3183 ,  G01R31/3167 ,  H03M1/10 ,  G06F17/50

Abstract: In one embodiment, a method of operating a computational system to evaluate a device under test, where the device under test is operable to receive a digital code input and output in response a corresponding output. The method injects a plurality of simulated faults into a pre-silicon model of the device under test. For each injected simulated fault, the method inputs a plurality of digital codes to the model. For each input digital code, the method selectively stores the input digital code if a difference, between a corresponding output for the input digital code and a no-fault output for the input, exceeds a predetermined threshold value.

公开(公告)号：US20160003900A1

公开(公告)日：2016-01-07

申请号：US14637543

申请日：2015-03-04

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Prakash Narayanan ,  Rubin Ajit Parekhji

IPC: G01R31/3177

CPC classification number: G01R31/318555 ,  G01R31/31724 ,  G01R31/318566 ,  G01R31/3187

Abstract: Circuits and methods for performing self-test of digital circuits are disclosed. In an embodiment, a method includes applying a set of test patterns for performing scan testing of a digital circuit to generate scan outputs from the digital circuit. The set of test patterns includes one or more sets of base test patterns already stored in a memory and one or more sets of derived test patterns temporarily generated from the one or more sets of base test patterns. The method further includes comparing the scan outputs received from the digital circuit with reference scan outputs corresponding to the digital circuit for fault detection in the digital circuit to thereby achieve a target fault coverage of the scan testing of the digital circuit. The reference scan outputs corresponding to the digital circuit are stored in the memory.

Abstract translation: 公开了用于执行数字电路自检的电路和方法。 在一个实施例中，一种方法包括应用一组用于执行数字电路的扫描测试以产生数字电路的扫描输出的测试图案。 该组测试模式包括已经存储在存储器中的一组或多组基本测试模式以及从一个或多个基本测试模式组临时生成的一组或多组派生测试模式。 该方法还包括将从数字电路接收的扫描输出与数字电路中用于故障检测的数字电路相对应的参考扫描输出进行比较，从而实现数字电路的扫描测试的目标故障覆盖。 对应于数字电路的参考扫描输出存储在存储器中。

公开(公告)号：US20150325308A1

公开(公告)日：2015-11-12

申请号：US14490170

申请日：2014-09-18

Applicant: Texas Instruments Incorporated

Inventor： Rajat Mehrotra ,  Rubin Ajit Parekhji ,  Maheedhar Jalasutram ,  Charu Shrimali

IPC: G11C16/34 ,  G11C29/12 ,  G11C16/14

CPC classification number: G11C16/3422 ,  G11C16/00 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/14 ,  G11C16/16 ,  G11C16/26 ,  G11C29/12 ,  G11C29/26 ,  G11C29/4401 ,  G11C2029/2602

Abstract: An apparatus for concurrent test of a set of flash memory banks apparatus includes a memory data path (MDP) module coupled to a test controller. The MDP module includes a test control module configured to generate a concurrent control signal that configures the set of flash memory banks to be tested simultaneously; and a set of comparators, that generates a first comparator output in response to the concurrent control signal and an input from the set of flash memory banks. A reduction logic is configured to generate a reduction logic output that combines a status of the comparator outputs to be compressed. A control logic is configured for selective programming across different flash bits of the set of flash memory banks. A fail flag is configured to generate one of an output value ‘0’ if there is a mismatch in data read from the set of flash memory banks in any access, and an output value 1 if there is no mismatch in data read in any access.

Abstract translation: 用于一组闪速存储器组装置的并发测试的装置包括耦合到测试控制器的存储器数据路径（MDP）模块。 MDP模块包括测试控制模块，其被配置为生成并发控制信号，其配置要同时测试的闪存组集合; 以及一组比较器，其响应于并发控制信号和来自闪存组的输入而产生第一比较器输出。 还原逻辑被配置为生成还原逻辑输出，其组合要压缩的比较器输出的状态。 控制逻辑被配置用于跨越闪存组的不同闪存位的选择性编程。 如果在任何访问中从闪存组中读取的数据不匹配，则失败标志被配置为产生输出值“0”，并且如果在任何访问中读取的数据不匹配，则输出值1 。

公开(公告)号：US08839063B2

公开(公告)日：2014-09-16

申请号：US13749623

申请日：2013-01-24

Applicant: Texas Instruments Incorporated

Inventor： Rubin Ajit Parekhji ,  Srivaths Ravi ,  Prakash Narayanan ,  Milan Shetty

IPC: G01R31/28 ,  G06F11/00

CPC classification number: G01R31/318544 ,  G01R31/318572

Abstract: A method of testing devices under test (DUTs) and testing system are disclosed. The method comprises generating at least one control signal associated with a test pattern structure received from a testing system. The method further comprises selecting M1 number of ports from M number of I/O ports in the DUT to receive scan input corresponding to the test pattern structure based on the control signal, selecting M2 number of ports from the M number of I/O ports to provide scan output based on the control signal, wherein each of M1 and M2 is a number selected from 0 to M, and wherein a sum of M1 and M2 is less than or equal to M. Thereafter, the method comprises performing a scan testing of the DUT based on the scan input provided to the M1 number of ports and receiving the scan output from the M2 number of ports.

Abstract translation: 公开了一种测试被测设备（DUT）和测试系统的方法。 该方法包括生成与从测试系统接收的测试图案结构相关联的至少一个控制信号。 该方法进一步包括从DUT中的M个I / O端口中选择M1个端口，以基于控制信号接收与测试模式结构相对应的扫描输入，从M个I / O端口中选择M2个端口 以提供基于控制信号的扫描输出，其中M1和M2中的每一个是从0到M中选择的数字，并且其中M1和M2的和小于或等于M.此后，该方法包括执行扫描测试 基于提供给M1端口的扫描输入并从M2端口接收扫描输出的DUT的DUT。

公开(公告)号：US11320478B2

公开(公告)日：2022-05-03

申请号：US16901966

申请日：2020-06-15

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Rubin Ajit Parekhji ,  Mahesh M. Mehendale ,  Vinod Menezes ,  Vipul K. Singhal

IPC: G01R33/00 ,  G01R31/28 ,  G01R31/3185 ,  G01R1/04 ,  G01R1/067

Abstract: In a method of testing a semiconductor wafer, a probe tip contacts a pad in a scribe line space between facing sides of first and second dies. The probe tip is electrically coupled to an automated test equipment (ATE). The second die is spaced apart from the first die. The scribe line space includes an interconnect extending along at least an entire length of the facing sides of the first and second dies. The pad is electrically coupled through the interconnect to at least one of the first or second dies. With the ATE, circuitry is tested in at least one of the first or second dies. The pad is electrically coupled through the interconnect to the circuitry.

公开(公告)号：US10684322B2

公开(公告)日：2020-06-16

申请号：US16247271

申请日：2019-01-14

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Rubin Ajit Parekhji ,  Mahesh M. Mehendale ,  Vinod Menezes ,  Vipul K. Singhal

IPC: G01R31/26 ,  G01R31/28 ,  G01R31/3185 ,  G01R1/04 ,  G01R1/067

Abstract: In a method of testing a semiconductor wafer including a scribe line and multiple dies, the method includes implementing a first landing pad on the scribe line, and implementing a first interconnect on the scribe line and between the first landing pad and a first cluster of the dies, thereby coupling the first landing pad to the first cluster of dies. The method also includes performing the testing of the first cluster of dies using automated test equipment (ATE) coupled to a probe tip by contacting the first landing pad with the probe tip, and applying an ATE resource to the first cluster of dies.

公开(公告)号：US10606723B2

公开(公告)日：2020-03-31

申请号：US14975193

申请日：2015-12-18

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Pankaj Bongale ,  Partha Ghosh ,  Rubin Ajit Parekhji

IPC: G06F11/00 ,  G06F11/263 ,  G06F11/24 ,  G01R31/28 ,  G06F11/22 ,  G06F11/273

Abstract: A test circuit that includes a circuit to be calibrated, an error generation circuit, and a simplex circuit coupled to one another. The circuit to be calibrated is configured to implement a first plurality of trim codes as calibration parameters for a corresponding plurality of components of the circuit to be calibrated and generate a first actual output. The error generation circuit is configured to generate a first error signal based on a difference between the first actual output and an expected output of the circuit to be calibrated. The simplex circuit is configured to receive the first error signal from the error generation circuit, generate a second plurality of trim codes utilizing a simplex algorithm based on the first error signal, and transmit the second plurality of trim codes to the circuit to be calibrated.