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    Power converter architecture using lower voltage power devices
    2.
    发明授权
    Power converter architecture using lower voltage power devices 有权

    公开(公告)号：US11387734B2

    公开(公告)日：2022-07-12

    申请号：US17024188

    申请日：2020-09-17

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Riazdeen Buhari ,  Roy Alan Hastings ,  Nghia Trong Tang

    IPC: H02M3/158 ,  H02M1/32

    Abstract: Aspects of the disclosure provide for a circuit. In at least some examples, the circuit includes a high-side power transistor, a low-side power transistor, a first transistor, a second transistor, and a third transistor. The high-side transistor is adapted to couple between an input node and a switch node. The low-side transistor is coupled between the switch node and ground. The first transistor is adapted to couple between a first node and the switch node. The second transistor is coupled between the first node and an output node. The third transistor is coupled between the first node and ground.

    Clock sync input dropout protection
    3.
    发明授权
    Clock sync input dropout protection 有权

    公开(公告)号：US11996686B2

    公开(公告)日：2024-05-28

    申请号：US17538479

    申请日：2021-11-30

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Chung San Roger Chan ,  John Mitchell Perry ,  Ari Arie Levy ,  Nghia Trong Tang

    IPC: G06F1/12 ,  G06F1/10 ,  H02H1/00 ,  H03K3/017

    CPC classification number: H02H1/0007 ,  G06F1/10 ,  G06F1/12 ,  H03K3/017

    Abstract: In a described example, a circuit includes a synchronization control circuit having a sync input and a sync control output, in which the sync input is coupled to a sync terminal configured to receive an external clock signal. An internal clock generator circuit has a control input and an output. The control input is coupled to the sync control output. An output circuit has first and second signal inputs, a mode control input and a clock output. The first signal input is coupled to the sync input, and the second signal input of the output circuit is coupled to the output of the internal clock generator circuit. The mode control input is coupled to the sync control output, and the clock output adapted to be coupled to a controller.

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