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公开(公告)号：US20210021122A1
公开(公告)日：2021-01-21
申请号：US16517019
申请日：2019-07-19
Applicant: Texas Instruments Incorporated
Inventor： Roy Alan Hastings
Abstract: Methods, apparatus, systems and articles of manufacture are disclosed for current sensing and current limiting. An example apparatus includes a first main transistor including a first main transistor gate terminal coupled between an output terminal and an intermediate node; a second main transistor including a second main transistor gate terminal coupled between the intermediate node and a ground terminal; a first amplifier including a first amplifier output coupled to the first main transistor gate terminal; a second amplifier including a second amplifier output coupled to the second main transistor gate terminal; and a third amplifier including a third amplifier inverting input coupled to the intermediate node, a third amplifier non-inverting input coupled to a sense transistor, and a third amplifier output coupled to a third gate terminal of a third transistor.
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公开(公告)号：US10734140B1
公开(公告)日：2020-08-04
申请号：US16286325
申请日：2019-02-26
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Roy Alan Hastings
Abstract: In an example, a device comprises a first resistor coupled to a second resistor and to a trim resistor, the second resistor and the trim resistor coupled to a port configured to couple to a third resistor. The device also comprises a comparator having an inverting input coupled to a first node between the second resistor and the port and a non-inverting input coupled to a second node between the first resistor and the trim resistor. The device further includes a trim control circuit coupled to an output of the comparator and having an output coupled to the trim resistor, the trim control circuit configured to couple to multiple integrated trim resistors external to the device.
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公开(公告)号：US20190310700A1
公开(公告)日：2019-10-10
申请号：US15949841
申请日：2018-04-10
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Deric Wayne Waters , Roy Alan Hastings
Abstract: In one embodiment, a system includes a power delivery (“PD”) controller in a USB Type-C system that includes a configuration channel (“CC”), PD preamble detector, and a power-usage circuit. The PD controller includes a CC input that receives a PD message. The PD preamble detector is configured to detect a PD message preamble based in part upon a power of a filtered PD message and communicates a wake-up signal to the power-usage circuit in response to detecting a PD message preamble. The power-usage circuit is configured to exit a low-power mode in response to receiving the wake-up signal.
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公开(公告)号：US09740261B2
公开(公告)日：2017-08-22
申请号：US14841119
申请日：2015-08-31
Applicant: Texas Instruments Incorporated
Inventor： Deric Wayne Waters , Roy Alan Hastings
CPC classification number: G06F1/30 , G06F1/266 , G06F1/3293
Abstract: A method of power delivery. Port controllers each include a state machine, an IO pin, a receptacle supply pin receiving power from a receptacle, and a gate driver pin coupled to a control node of a power path switch each having an output coupled to a load. The state machines implement a dead-battery control (DBC) algorithm upon sensing a DB condition. The DBC algorithm pulls up the IO pin, starts a timer for T1, and monitors the IO pin for T1. If the IO pin is pulled low, the port controller is reset for a pulled low period, the DBC algorithm is then restarted or its IO pin is monitored until not pulled low for T1. One port controller pulls its IO pin low for an assertion period to claim priority over the other port controller, and closes its associated power path switch to exclusively provide power to the load.
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公开(公告)号：US11770118B2
公开(公告)日：2023-09-26
申请号：US17093677
申请日：2020-11-10
Applicant: Texas Instruments Incorporated
Inventor： Deric Wayne Waters , Roy Alan Hastings
IPC: G06F1/3296 , H03H7/06 , G06F1/28 , G06F1/3206 , H02J7/00 , H03K5/24
CPC classification number: H03K5/24 , G06F1/28 , G06F1/3206 , G06F1/3296 , H03H7/06 , H02J7/00 , H02J7/00034
Abstract: In one embodiment, a system includes a power delivery (“PD”) controller in a USB Type-C system that includes a configuration channel (“CC”), PD preamble detector, and a power-usage circuit. The PD controller includes a CC input that receives a PD message. The PD preamble detector is configured to detect a PD message preamble based in part upon a power of a filtered PD message and communicates a wake-up signal to the power-usage circuit in response to detecting a PD message preamble. The power-usage circuit is configured to exit a low-power mode in response to receiving the wake-up signal.
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Patent Agency Ranking
公开(公告)号：US20230019385A1
公开(公告)日：2023-01-19
申请号：US17935260
申请日：2022-09-26
Applicant: Texas Instruments Incorporated
Inventor： Roy Alan Hastings
Abstract: A sectioned field effect transistor (“FET”) for implementing a rapidly changing sense range ratio dynamically in response to changing load and main supply conditions. The sectioned FET may have multiple main FET sections, and multiple sense FET sections. These sections can be dynamically connected and disconnected from the sectioned FET. The sections may also be connected by a common gate. There may also be common drain or source connections for the main FET sections, and also common drain or source connections for the sense FET sections. The sectioned FET allows for the sense range to be extended by a multiple of k+1, where k is the size ratio or factor of the additional sense FET sections. This allows the current sense range ratio to be extended to (m+n)/n*(k+1).
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公开(公告)号：US11239656B2
公开(公告)日：2022-02-01
申请号：US16517019
申请日：2019-07-19
Applicant: Texas Instruments Incorporated
Inventor： Roy Alan Hastings
IPC: H02H9/02 , H02H1/00 , G01R19/165
Abstract: Methods, apparatus, systems and articles of manufacture are disclosed for current sensing and current limiting. An example apparatus includes a first main transistor including a first main transistor gate terminal coupled between an output terminal and an intermediate node; a second main transistor including a second main transistor gate terminal coupled between the intermediate node and a ground terminal; a first amplifier including a first amplifier output coupled to the first main transistor gate terminal; a second amplifier including a second amplifier output coupled to the second main transistor gate terminal; and a third amplifier including a third amplifier inverting input coupled to the intermediate node, a third amplifier non-inverting input coupled to a sense transistor, and a third amplifier output coupled to a third gate terminal of a third transistor.
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公开(公告)号：US10574139B2
公开(公告)日：2020-02-25
申请号：US16228191
申请日：2018-12-20
Applicant: Texas Instruments Incorporated
Inventor： Roy Alan Hastings
Abstract: A reference signal generator includes a voltage reference, an amplifier coupled to the voltage reference, and a precharge circuit coupled to the amplifier. The voltage reference is configured to generate a constant voltage. The amplifier is configured to receive the constant voltage from the voltage reference and generate a regulating primary output signal and a non-regulating secondary output signal. The precharge circuit is configured to charge a noise reduction capacitor with the non-regulating secondary output signal.
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公开(公告)号：US11387734B2
公开(公告)日：2022-07-12
申请号：US17024188
申请日：2020-09-17
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Riazdeen Buhari , Roy Alan Hastings , Nghia Trong Tang
Abstract: Aspects of the disclosure provide for a circuit. In at least some examples, the circuit includes a high-side power transistor, a low-side power transistor, a first transistor, a second transistor, and a third transistor. The high-side transistor is adapted to couple between an input node and a switch node. The low-side transistor is coupled between the switch node and ground. The first transistor is adapted to couple between a first node and the switch node. The second transistor is coupled between the first node and an output node. The third transistor is coupled between the first node and ground.
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公开(公告)号：US20210041486A1
公开(公告)日：2021-02-11
申请号：US17077404
申请日：2020-10-22
Applicant: Texas Instruments Incorporated
Inventor： Roy Alan Hastings
Abstract: A sectioned field effect transistor (“FET”) for implementing a rapidly changing sense range ratio dynamically in response to changing load and main supply conditions. The sectioned FET may have multiple main FET sections, and multiple sense FET sections. These sections can be dynamically connected and disconnected from the sectioned FET. The sections may also be connected by a common gate. There may also be common drain or source connections for the main FET sections, and also common drain or source connections for the sense FET sections. The sectioned FET allows for the sense range to be extended by a multiple of k+1, where k is the size ratio or factor of the additional sense FET sections. This allows the current sense range ratio to be extended to (m+n)/n*(k+1).
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