公开(公告)号：US11740208B2

公开(公告)日：2023-08-29

申请号：US17350552

申请日：2021-06-17

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Prashuk Jain ,  Ravikumar Pattipaka ,  Vajeed Nimran Parambil Abdul Raheem ,  Sandeep Kesrimal Oswal

IPC: G01S7/52 ,  G01N29/24 ,  G06F7/58 ,  G01S7/491 ,  G01N29/36

CPC classification number: G01N29/2468 ,  G01N29/36 ,  G01S7/491 ,  G01S7/5208 ,  G01S7/52023 ,  G01S7/52095 ,  G06F7/582

Abstract: A delay line control circuit includes a pseudo-random number generator and a random phase generator circuit coupled to the pseudo-random number generator. The pseudo-random number generator is configured to produce a predetermined sequence of pseudo-random values. The random phase generator circuit is configured to randomize an access sequence for capacitors of a delay line. The random phase generator circuit includes a sequence register, an adder, and gating circuitry. The sequence register is configured to a store a value identifying one of the capacitors to be accessed. The adder is coupled to the sequence register, and is configured to increment the value stored in sequence register. The gating circuitry is coupled to the pseudo-random number generator and the adder. The gating circuitry is configured to pass one of the pseudo-random values to the adder for addition to the value stored in the sequence register.

公开(公告)号：US11067544B2

公开(公告)日：2021-07-20

申请号：US16220001

申请日：2018-12-14

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Prashuk Jain ,  Ravikumar Pattipaka ,  Vajeed Nimran Parambil Abdul Raheem ,  Sandeep Kesrimal Oswal

IPC: G01N29/24 ,  G01S7/52 ,  G06F7/58 ,  G01S7/491 ,  G01N29/36

Abstract: A delay line control circuit includes a pseudo-random number generator and a random phase generator circuit coupled to the pseudo-random number generator. The pseudo-random number generator is configured to produce a predetermined sequence of pseudo-random values. The random phase generator circuit is configured to randomize an access sequence for capacitors of a delay line. The random phase generator circuit includes a sequence register, an adder, and gating circuitry. The sequence register is configured to a store a value identifying one of the capacitors to be accessed. The adder is coupled to the sequence register, and is configured to increment the value stored in sequence register. The gating circuitry is coupled to the pseudo-random number generator and the adder. The gating circuitry is configured to pass one of the pseudo-random values to the adder for addition to the value stored in the sequence register.

公开(公告)号：US20240171144A1

公开(公告)日：2024-05-23

申请号：US17990682

申请日：2022-11-19

Applicant: Texas Instruments Incorporated

Inventor： Ravikumar Pattipaka ,  Prashuk Jain ,  Vajeed Nimran

IPC: H03F3/45

CPC classification number: H03F3/45928 ,  H03F3/45076 ,  H03F2200/231 ,  H03F2200/294

Abstract: A differential to single-ended summation circuit includes a first switch which includes a first terminal coupled to a first circuit input and includes a second terminal. The circuit includes a second switch which includes a first terminal coupled to a second circuit input and includes a second terminal. The circuit includes a holding capacitor which includes a first terminal coupled to the second terminal of the first switch and a second terminal coupled to the second terminal of the second switch. The circuit includes a third switch which includes a first terminal coupled to the second terminal of the first switch and a second terminal coupled to a circuit output. The circuit includes a fourth switch including a first terminal coupled to the second terminal of the second switch and a second terminal coupled to a common potential.

公开(公告)号：US20250007484A1

公开(公告)日：2025-01-02

申请号：US18217325

申请日：2023-06-30

Applicant: Texas Instruments Incorporated

Inventor： Raja Sekhar ,  Prashuk Jain ,  Sandeep Oswal ,  Ravikumar Pattipaka

IPC: H03H7/01 ,  H04B1/04

Abstract: Methods, apparatus, systems, and articles of manufacture are described corresponding to current limit circuitry with controlled current variation. An example circuit includes an amplifier having an input terminal and an output terminal; a capacitor having a first terminal and a second terminal, the first terminal of the capacitor coupled to the input terminal of the amplifier, the second terminal of the capacitor coupled to the output terminal of the amplifier; and diode circuitry having a first terminal and a second terminal, the first terminal of the diode circuitry coupled to the first terminal of the capacitor and the input terminal of the amplifier, the second terminal of the diode circuitry coupled to the second terminal of the capacitor and the output terminal of the amplifier.