公开(公告)号：US11704154B2

公开(公告)日：2023-07-18

申请号：US17359749

申请日：2021-06-28

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Thomas Anton Leyrer ,  William Cronin Wallace ,  Pratheesh Gangadhar Thalakkal Kottilaveedu ,  David Alston Lide

IPC: G06F9/48 ,  G06F13/28 ,  G06F13/40 ,  G06F16/9035 ,  G06F9/52 ,  G06F9/50 ,  G06F1/06 ,  G06F13/20 ,  G06F9/448 ,  G06F11/10 ,  H04L1/00

CPC classification number: G06F9/4881 ,  G06F1/06 ,  G06F9/448 ,  G06F9/5011 ,  G06F9/5016 ,  G06F9/5038 ,  G06F9/52 ,  G06F11/1004 ,  G06F13/20 ,  G06F13/28 ,  G06F13/4068 ,  G06F16/9035 ,  H04L1/0041 ,  G06F2209/503 ,  G06F2209/5012

Abstract: A real-time computational device includes a programmable real-time processor, a communications input port which is connected to the programmable real-time processor through a first broadside interface, and a communications output port which is connected to the programmable real-time processor through a second broadside interface. Both broadside interfaces enable 1024 bits of data to be transferred across each of the broadside interfaces in a single clock cycle of the programmable real-time processor.

公开(公告)号：US11726814B2

公开(公告)日：2023-08-15

申请号：US16425678

申请日：2019-05-29

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Anjandeep Singh Sahni ,  Pratheesh Gangadhar Thalakkal Kottilaveedu ,  William Cronin Wallace

IPC: G06F9/48 ,  G06F9/52 ,  G06F9/50 ,  G06F9/448 ,  G06F16/9035 ,  G06F1/06 ,  G06F13/20 ,  G06F13/28 ,  G06F13/40 ,  G06F11/10 ,  H04L1/00

CPC classification number: G06F9/4881 ,  G06F1/06 ,  G06F9/448 ,  G06F9/5011 ,  G06F9/5016 ,  G06F9/5038 ,  G06F9/52 ,  G06F11/1004 ,  G06F13/20 ,  G06F13/28 ,  G06F13/4068 ,  G06F16/9035 ,  H04L1/0041 ,  G06F2209/503 ,  G06F2209/5012

Abstract: A computing resource allocation method comprises beginning a first performance of a first task; determining, using a task manager circuit during the first performance of the first task, that a first operation from among the first plurality of operations requires a resource, wherein the resource is external to the processor; determining, using a spinlock circuit, that the resource is unavailable for use; pausing, under control of the task manager, the first performance of the first task at the processor; beginning, using the processor, a second performance of a second task, the second task comprising a second plurality of operations; receiving, at the task manager, a notice from the spinlock that the resource is currently available for use by the processor; and resuming, under control of the task manager, the first performance of the first task at the processor starting with the first operation from among the first plurality of operations.

公开(公告)号：US20140101383A1

公开(公告)日：2014-04-10

申请号：US14045995

申请日：2013-10-04

Applicant: Texas Instruments Incorporated

Inventor： Pratheesh Gangadhar Thalakkal Kottilaveedu ,  William C. Wallace

IPC: G11C7/10

CPC classification number: G11C7/1036 ,  G06F9/3012 ,  G11C8/04

Abstract: Scratch pad register banks are used as shared fast access storage between processors in a multi processor system. Instead of the usual one to one register mapping between the processors and the scratch pad register banks, an any to any mapping is implemented. The utilization of the scratch pad register banks is improved as the any to any mapping of the registers allow the storage of any processor register anywhere in the scratch pad register bank.

Abstract translation: 划痕寄存器组用作多处理器系统中的处理器之间的共享快速存取存储。 代替处理器和暂存寄存器组之间通常的一对一寄存器映射，实现任何到任何映射。 缓冲寄存器组的使用得到改善，因为对寄存器的任何映射允许将任何处理器寄存器存储在暂存器寄存器组中的任何地方。

公开(公告)号：US11579877B2

公开(公告)日：2023-02-14

申请号：US17223103

申请日：2021-04-06

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Thomas Anton Leyrer ,  William Cronin Wallace ,  David Alston Lide ,  Pratheesh Gangadhar Thalakkal Kottilaveedu

IPC: G06F9/30 ,  G06F3/06 ,  G06F9/38 ,  G06F12/0875 ,  G06F9/48 ,  G06F30/34

Abstract: A computational system includes one or more processors. Each processor has multiple registers, as well attached memory to hold instructions. The processor is coupled to one or more broadside interfaces. A broadside interface allows the processor to load or store an entire widget state in a single clock cycle of the processor. The broadside interface also allows the processor to move and store 32 bytes of information into RAM in less than four to five clock cycles of the processor while the processor concurrently performs one or more mathematical operations on the information while the move and store operation is taking place.

公开(公告)号：US11048552B2

公开(公告)日：2021-06-29

申请号：US16425606

申请日：2019-05-29

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Thomas Anton Leyrer ,  William Cronin Wallace ,  Pratheesh Gangadhar Thalakkal Kottilaveedu ,  David Alston Lide

IPC: G06F9/48 ,  G06F13/28 ,  G06F13/40 ,  G06F16/9035 ,  G06F9/52 ,  G06F9/50 ,  G06F1/06 ,  G06F13/20 ,  G06F9/448 ,  G06F11/10 ,  H04L1/00

Abstract: A real-time computational device includes a programmable real-time processor, a communications input port which is connected to the programmable real-time processor through a first broadside interface, and a communications output port which is connected to the programmable real-time processor through a second broadside interface. Both broadside interfaces enable 1024 bits of data to be transferred across each of the broadside interfaces in a single clock cycle of the programmable real-time processor.

公开(公告)号：US11343205B2

公开(公告)日：2022-05-24

申请号：US16425734

申请日：2019-05-29

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Thomas Anton Leyrer ,  William Cronin Wallace ,  Pratheesh Gangadhar Thalakkal Kottilaveedu

IPC: H04L49/25 ,  G05B19/4155 ,  H04L43/16 ,  H04L45/74 ,  H04L47/32

Abstract: An ultra-high speed electronic communications device includes: a network communications interface; a memory; and one or more processing units, communicatively coupled to the memory and the network communications interface, wherein the memory stores instructions configured to cause the one or more processing units to: receive a data packet using the network communications interface; determine a classification of the data packet based, at least in part, on a plurality of factors, wherein the plurality of factors comprises a rate at which the data packet was received and a time at which the data packet was received; select, based at least in part, on the classification, an operation from a plurality of operations, wherein the plurality of operations comprises a cut-through operation and a store-and-forward operation; and perform the selected operation.

公开(公告)号：US09153295B2

公开(公告)日：2015-10-06

申请号：US14045995

申请日：2013-10-04

Applicant: Texas Instruments Incorporated

Inventor： Pratheesh Gangadhar Thalakkal Kottilaveedu ,  William C Wallace

IPC: G06F13/12 ,  G06F13/00 ,  G11C7/10 ,  G11C8/04 ,  G06F9/30

CPC classification number: G11C7/1036 ,  G06F9/3012 ,  G11C8/04

Abstract: Scratch pad register banks are used as shared fast access storage between processors in a multi processor system. Instead of the usual one to one register mapping between the processors and the scratch pad register banks, an any to any mapping is implemented. The utilization of the scratch pad register banks is improved as the any to any mapping of the registers allow the storage of any processor register anywhere in the scratch pad register bank.

Abstract translation: 划痕寄存器组用作多处理器系统中的处理器之间的共享快速存取存储。 代替处理器和暂存寄存器组之间通常的一对一寄存器映射，实现任何到任何映射。 缓冲寄存器组的使用得到改善，因为对寄存器的任何映射允许将任何处理器寄存器存储在暂存器寄存器组中的任何地方。

公开(公告)号：US09047188B2

公开(公告)日：2015-06-02

申请号：US14046048

申请日：2013-10-04

Applicant: Texas Instruments Incorporated

Inventor： Pratheesh Gangadhar Thalakkal Kottilaveedu ,  Kanad D. Kanhere

IPC: G06F3/00 ,  G06F11/07

CPC classification number: G06F11/0745 ,  H04L12/40013

Abstract: In the L2 FIFO architecture incoming frames are stored in a multi bank FIFO to enable offloading the programmable real-time unit to do other tasks. The L2 FIFO buffers data coming from the L1 FIFO, reducing the polling time for received data. Status is always checked for errors before processing the data and updating the state variables. Implementing a state machine to perform some of the checks results in a PRU utilization that is not a function of the bytes that need to be processed.

Abstract translation: 在L2 FIFO架构中，输入帧存储在多存储体FIFO中，以实现对可编程实时单元的卸载以执行其他任务。 L2 FIFO缓冲来自L1 FIFO的数据，减少了接收数据的轮询时间。 在处理数据和更新状态变量之前，始终检查状态是否有错误。 执行状态机来执行某些检查会导致PRU利用率不是需要处理的字节的函数。

公开(公告)号：US20140101496A1

公开(公告)日：2014-04-10

申请号：US14046048

申请日：2013-10-04

Applicant: Texas Instruments Incorporated

Inventor： Pratheesh Gangadhar Thalakkal Kottilaveedu ,  Kanad D. Kanhere

IPC: G06F11/07

CPC classification number: G06F11/0745 ,  H04L12/40013

Abstract: In the L2 FIFO architecture incoming frames are stored in a multi bank FIFO to enable offloading the programmable real-time unit to do other tasks. The L2 FIFO buffers data coming from the L1 FIFO, reducing the polling time for received data. Status is always checked for errors before processing the data and updating the state variables. Implementing a state machine to perform some of the checks results in a PRU utilization that is not a function of the bytes that need to be processed.

Abstract translation: 在L2 FIFO架构中，输入帧存储在多存储体FIFO中，以实现对可编程实时单元的卸载，以执行其他任务。 L2 FIFO缓冲来自L1 FIFO的数据，减少了接收数据的轮询时间。 在处理数据和更新状态变量之前，始终检查状态是否有错误。 执行状态机来执行某些检查会导致PRU利用率不是需要处理的字节的函数。