公开(公告)号：US20200228127A1

公开(公告)日：2020-07-16

申请号：US16828149

申请日：2020-03-24

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Raja Reddy PATUKURI ,  Jagannathan VENKATARAMAN ,  Shagun DUSAD

IPC: H03M1/08 ,  H04B1/40 ,  H03M1/10

Abstract: A transceiver system includes a clock generator and an analog-to-digital circuit (ADC). The transceiver system also includes a coupling correction circuit coupled to the clock generator and to the ADC, wherein the coupling correction circuit is configured to provide an in-phase correction and a quadrature-phase correction to a signal received by the ADC.

公开(公告)号：US20240313751A1

公开(公告)日：2024-09-19

申请号：US18589715

申请日：2024-02-28

Applicant: Texas Instruments Incorporated

Inventor： Sachin AITHAL ,  Anand H UDUPA ,  Raja Reddy PATUKURI ,  Sandeep OSWAL ,  Aatish CHANDAK ,  Vignesh SUBRAMANYA ,  Aravind MIRIYALA

IPC: H03K5/1252 ,  A61B5/00 ,  A61B5/349 ,  H03M1/12

CPC classification number: H03K5/1252 ,  A61B5/349 ,  A61B5/7217 ,  H03M1/12

Abstract: A circuit includes an interference frequency tracking circuit, a PLI synthesizer circuit, and a summing circuit. The interference frequency tracking circuit is configured to track a frequency of an interference signal derived from a target signal, and provide a frequency selection value representing the frequency of the interference signal. The PLI synthesizer circuit is configured to generate, based on the frequency selection value, a correction signal at the frequency of the interference signal, adjust a phase of the correction signal to match a phase of the interference signal in the target signal, and adjust an amplitude of the correction signal to match an amplitude of the interference signal in the target signal. The summing circuit is configured to subtract the correction signal from the target signal.

公开(公告)号：US20160329906A1

公开(公告)日：2016-11-10

申请号：US14852104

申请日：2015-09-11

Applicant: Texas Instruments Incorporated

Inventor： Raja Reddy PATUKURI ,  Jagannathan Venkataraman ,  Prabu Sankar Thirugnanam

IPC: H03M1/12 ,  G01S7/486 ,  G01S17/02

CPC classification number: G01S7/4865 ,  G01S7/4863 ,  G01S17/89 ,  H03M1/00 ,  H03M1/1245 ,  H03M1/1295 ,  H03M1/164 ,  H03M1/361

Abstract: The disclosure provides a circuit. The circuit includes a first analog to digital converter (ADC) that generates a coarse output in response to a first input and a second input. The first ADC generates the coarse output in a differential phase. A pipeline ADC generates a differential signal in response to the coarse output, the first input and the second input. The pipeline ADC generates the differential signal in a common-mode phase. The first ADC generates a common mode signal in the common-mode phase.

Abstract translation: 本公开提供一种电路。 电路包括响应于第一输入和第二输入而产生粗略输出的第一模数转换器（ADC）。 第一个ADC在差分相位产生粗略输出。 流水线ADC响应于粗略输出（第一输入和第二输入）产生差分信号。 流水线ADC在共模相位产生差分信号。 第一个ADC在共模相位产生共模信号。

公开(公告)号：US20150377964A1

公开(公告)日：2015-12-31

申请号：US14755728

申请日：2015-06-30

Applicant: Texas Instruments Incorporated

Inventor： Raja Reddy PATUKURI ,  Jagannathan Venkataraman

IPC: G01R31/3187 ,  G01S17/02 ,  H04N17/00

CPC classification number: G01S17/02 ,  G01S7/4863 ,  G01S7/497 ,  H04N17/002

Abstract: The disclosure provides a circuit capable of generating programmable test patterns for a pixel array. The circuit includes a pixel array having a plurality of pixels arranged in a plurality of rows and a plurality of columns. A built-in-tester is coupled to the pixel array. The built-in-tester includes a data pattern register that generates a plurality of test patterns. A switching logic circuit is coupled between the data pattern register and the pixel array. The switching logic circuit provides to each column of the plurality of columns one of a first voltage and a second voltage based on a test pattern of the plurality of test patterns received from the data pattern register.

Abstract translation: 本公开提供了一种能够产生像素阵列的可编程测试图案的电路。 电路包括具有以多行排列的多个像素和多列的像素阵列。 内置测试仪耦合到像素阵列。 内置测试器包括产生多个测试图案的数据模式寄存器。 开关逻辑电路耦合在数据模式寄存器和像素阵列之间。 基于从数据模式寄存器接收的多个测试模式的测试模式，开关逻辑电路向多列的每列提供第一电压和第二电压之一。