公开(公告)号：US10855069B2

公开(公告)日：2020-12-01

申请号：US15955214

申请日：2018-04-17

Applicant: Texas Instruments Incorporated

Inventor： Rajdeep Mukhopadhyay ,  Pulkit Shah ,  Vinod Joseph Menezes

IPC: H02H3/26 ,  H03K17/687 ,  G06F13/40 ,  H03K5/24 ,  H01R13/66

Abstract: A USB Type-C/Power Delivery controller chip includes a first pin for receiving a first voltage, a second pin for receiving a second voltage, and a third pin for coupling to the CC pin of a USB connector. The USB controller chip includes a VCONN power supply circuit having a blocking field effect transistor (BFET) coupled in series with a hot-swap field FET (HSFET) between the first and third pins, and first and second Zener diodes coupled anode-to-anode between the HSFET's source and gate. A cable detection circuit includes a BFET coupled between the second and third pins, and a Zener diode coupled between the BFET's gate and a lower rail. A power delivery physical layer circuit includes a receiver and a transmitter, each coupled to the third pin through a respective BFET, the respective BFETs each having a Zener diode coupled between respective gates and the lower rail.

公开(公告)号：US20190319447A1

公开(公告)日：2019-10-17

申请号：US15955214

申请日：2018-04-17

Applicant: Texas Instruments Incorporated

Inventor： Rajdeep Mukhopadhyay ,  PuIkit Shah ,  Vinod Joseph Menezes

IPC: H02H3/26 ,  H03K17/687 ,  H03K5/24 ,  G06F13/40

Abstract: A USB Type-C/Power Delivery controller chip includes a first pin for receiving a first voltage, a second pin for receiving a second voltage, and a third pin for coupling to the CC pin of a USB connector. The USB controller chip includes a VCONN power supply circuit having a blocking field effect transistor (BFET) coupled in series with a hot-swap field FET (HSFET) between the first and third pins, and first and second Zener diodes coupled anode-to-anode between the HSFET's source and gate. A cable detection circuit includes a BFET coupled between the second and third pins, and a Zener diode coupled between the BFET's gate and a lower rail. A power delivery physical layer circuit includes a receiver and a transmitter, each coupled to the third pin through a respective BFET, the respective BFETs each having a Zener diode coupled between respective gates and the lower rail.

公开(公告)号：US20220263309A1

公开(公告)日：2022-08-18

申请号：US17738828

申请日：2022-05-06

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Rajdeep Mukhopadhyay ,  Pulkit Shah ,  Vinod Joseph Menezes

IPC: H02H3/26 ,  H03K17/687 ,  G06F13/40 ,  H03K5/24

Abstract: A USB Type-C/Power Delivery controller chip includes a first pin for receiving a first voltage, a second pin for receiving a second voltage, and a third pin for coupling to the CC pin of a USB connector. The USB controller chip includes a VCONN power supply circuit having a blocking field effect transistor (BFET) coupled in series with a hot-swap field FET (HSFET) between the first and third pins, and first and second Zener diodes coupled anode-to-anode between the HSFET's source and gate. A cable detection circuit includes a BFET coupled between the second and third pins, and a Zener diode coupled between the BFET's gate and a lower rail. A power delivery physical layer circuit includes a receiver and a transmitter, each coupled to the third pin through a respective BFET, the respective BFETs each having a Zener diode coupled between respective gates and the lower rail.

公开(公告)号：US11355918B2

公开(公告)日：2022-06-07

申请号：US17078425

申请日：2020-10-23

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Rajdeep Mukhopadhyay ,  Pulkit Shah ,  Vinod Joseph Menezes

IPC: H02H3/26 ,  H03K17/687 ,  G06F13/40 ,  H03K5/24 ,  H01R13/66

Abstract: A USB Type-C/Power Delivery controller chip includes a first pin for receiving a first voltage, a second pin for receiving a second voltage, and a third pin for coupling to the CC pin of a USB connector. The USB controller chip includes a VCONN power supply circuit having a blocking field effect transistor (BFET) coupled in series with a hot-swap field FET (HSFET) between the first and third pins, and first and second Zener diodes coupled anode-to-anode between the HSFET's source and gate. A cable detection circuit includes a BFET coupled between the second and third pins, and a Zener diode coupled between the BFET's gate and a lower rail. A power delivery physical layer circuit includes a receiver and a transmitter, each coupled to the third pin through a respective BFET, the respective BFETs each having a Zener diode coupled between respective gates and the lower rail.

公开(公告)号：US20210044101A1

公开(公告)日：2021-02-11

申请号：US17078425

申请日：2020-10-23

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Rajdeep Mukhopadhyay ,  Pulkit Shah ,  Vinod Joseph Menezes

IPC: H02H3/26 ,  H03K17/687 ,  G06F13/40 ,  H03K5/24

Abstract: A USB Type-C/Power Delivery controller chip includes a first pin for receiving a first voltage, a second pin for receiving a second voltage, and a third pin for coupling to the CC pin of a USB connector. The USB controller chip includes a VCONN power supply circuit having a blocking field effect transistor (BFET) coupled in series with a hot-swap field FET (HSFET) between the first and third pins, and first and second Zener diodes coupled anode-to-anode between the HSFET's source and gate. A cable detection circuit includes a BFET coupled between the second and third pins, and a Zener diode coupled between the BFET's gate and a lower rail. A power delivery physical layer circuit includes a receiver and a transmitter, each coupled to the third pin through a respective BFET, the respective BFETs each having a Zener diode coupled between respective gates and the lower rail.

公开(公告)号：US20150288178A1

公开(公告)日：2015-10-08

申请号：US14672420

申请日：2015-03-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sanjay Gurlahosur ,  Rajdeep Mukhopadhyay

IPC: H02J1/10 ,  G05F1/62

CPC classification number: H02J1/102 ,  Y10T307/675

Abstract: A power controller that includes first and second buck controllers and a power balancer. The first buck controller is configured to receive a first power rail at a first voltage and generate a first output signal. The second buck controller is configured to receive a second power rail at a second voltage and generate a second output signal. The power balancer is configured to receive an average current for the output signals and generate, based on the average current, a reference voltage to be received by the second buck controller. The output signals are combined to create a output power rail such that the first buck controller functions as a voltage source for the output power rail and the second buck controller controls, based on the reference voltage, an amount of current in the output power rail received from each of the buck controllers.

Abstract translation: 一个功率控制器，包括第一和第二降压控制器和电源平衡器。 第一降压控制器被配置为以第一电压接收第一电力轨并产生第一输出信号。 第二降压控制器被配置为以第二电压接收第二电力轨并产生第二输出信号。 功率平衡器被配置为接收输出信号的平均电流，并且基于平均电流生成要由第二降压控制器接收的参考电压。 输出信号被组合以产生输出电力轨，使得第一降压控制器用作输出电力轨的电​​压源，而第二降压控制器基于参考电压控制所接收的输出功率轨中的电流量 从每个降压控制器。

公开(公告)号：US11848552B2

公开(公告)日：2023-12-19

申请号：US17738828

申请日：2022-05-06

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Rajdeep Mukhopadhyay ,  Pulkit Shah ,  Vinod Joseph Menezes

IPC: H02H3/26 ,  H03K17/687 ,  G06F13/40 ,  H03K5/24 ,  H01R13/66 ,  H02H9/02 ,  H02H9/04

CPC classification number: H02H3/26 ,  G06F13/4081 ,  H03K5/24 ,  H03K17/687 ,  G06F2213/0042 ,  H01R13/6675 ,  H02H9/02 ,  H02H9/04

Abstract: A USB Type-C/Power Delivery controller chip includes a first pin for receiving a first voltage, a second pin for receiving a second voltage, and a third pin for coupling to the CC pin of a USB connector. The USB controller chip includes a VCONN power supply circuit having a blocking field effect transistor (BFET) coupled in series with a hot-swap field FET (HSFET) between the first and third pins, and first and second Zener diodes coupled anode-to-anode between the HSFET's source and gate. A cable detection circuit includes a BFET coupled between the second and third pins, and a Zener diode coupled between the BFET's gate and a lower rail. A power delivery physical layer circuit includes a receiver and a transmitter, each coupled to the third pin through a respective BFET, the respective BFETs each having a Zener diode coupled between respective gates and the lower rail.

公开(公告)号：US10476266B2

公开(公告)日：2019-11-12

申请号：US14672420

申请日：2015-03-30

Applicant: Texas Instruments Incorporated

Inventor： Sanjay Gurlahosur ,  Rajdeep Mukhopadhyay

IPC: H02J1/10

Abstract: A power controller that includes first and second buck controllers and a power balancer. The first buck controller is configured to receive a first power rail at a first voltage and generate a first output signal. The second buck controller is configured to receive a second power rail at a second voltage and generate a second output signal. The power balancer is configured to receive an average current for the output signals and generate, based on the average current, a reference voltage to be received by the second buck controller. The output signals are combined to create a output power rail such that the first buck controller functions as a voltage source for the output power rail and the second buck controller controls, based on the reference voltage, an amount of current in the output power rail received from each of the buck controllers.