公开(公告)号：US10120674B2

公开(公告)日：2018-11-06

申请号：US15139865

申请日：2016-04-27

Applicant: Texas Instruments Incorporated

Inventor： Ralf Brederlow ,  Oscar Miguel Guillen-Hernandez ,  Peter Wongeun Chung

IPC: G11C11/22 ,  G06F8/65

Abstract: An integrated circuit including a ferroelectric random access memory (FRAM) for storing firmware, and a method of updating that firmware. The FRAM is constructed to selectively operate as a 2T2C FRAM memory in a normal operating mode, and as a 1T1C FRAM memory in an update mode. Updating of the stored firmware is performed by placing the FRAM in its update (1T1C) mode and writing the updated code into alternate rows of the 1T1C half-cells at each of a plurality of memory locations, while the other 1T1C half-cells in the other alternate rows retain the original data. Following verification of the updated contents, the original data in the other half-cells are overwritten with the verified updated data, and the operating mode is changed back to the normal (2T2C) operating mode.

公开(公告)号：US10763833B2

公开(公告)日：2020-09-01

申请号：US16235291

申请日：2018-12-28

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Ernst Gerog Muellner ,  Tobias Fritz ,  Bradley Kramer ,  Swaminathan Sankaran ,  Baher Haroun ,  Ralf Brederlow

IPC: H03K3/03 ,  H03K3/014

Abstract: In described examples, a ring oscillator includes a series of N stages in a first ring. Each stage includes a respective output terminal coupled to a respective input terminal of a next one of the stages in the first ring. N is a positive odd-numbered integer of at least three. A series of N level shifters in a second ring are respectively connected to the N stages. Each level shifter receives a respective clock output from a respective output terminal of a stage to which it is connected and generates a respective boosted clock output in response thereto. The boosted clock output is coupled to control an impedance state of a next one of the level shifters in the second ring.

公开(公告)号：US10545752B2

公开(公告)日：2020-01-28

申请号：US16182138

申请日：2018-11-06

Applicant: Texas Instruments Incorporated

Inventor： Ralf Brederlow ,  Oscar Miguel Guillen-Hernandez ,  Peter Wongeun Chung

IPC: G11C11/22 ,  G06F8/65

Abstract: An integrated circuit including a ferroelectric random access memory (FRAM) for storing firmware, and a method of updating that firmware. The FRAM is constructed to selectively operate as a 2T2C FRAM memory in a normal operating mode, and as a 1T1C FRAM memory in an update mode. Updating of the stored firmware is performed by placing the FRAM in its update (1T1C) mode and writing the updated code into alternate rows of the 1T1C half-cells at each of a plurality of memory locations, while the other 1T1C half-cells in the other alternate rows retain the original data. Following verification of the updated contents, the original data in the other half-cells are overwritten with the verified updated data, and the operating mode is changed back to the normal (2T2C) operating mode.

公开(公告)号：US20190087171A1

公开(公告)日：2019-03-21

申请号：US16182138

申请日：2018-11-06

Applicant: Texas Instruments Incorporated

Inventor： Ralf Brederlow ,  Oscar Miguel Guillen-Hernandez ,  Peter Wongeun Chung

IPC: G06F8/65 ,  G11C11/22

CPC classification number: G06F8/65 ,  G11C11/221 ,  G11C11/225 ,  G11C11/2253

Abstract: An integrated circuit including a ferroelectric random access memory (FRAM) for storing firmware, and a method of updating that firmware. The FRAM is constructed to selectively operate as a 2T2C FRAM memory in a normal operating mode, and as a 1T1C FRAM memory in an update mode. Updating of the stored firmware is performed by placing the FRAM in its update (1T1C) mode and writing the updated code into alternate rows of the 1T1C half-cells at each of a plurality of memory locations, while the other 1T1C half-cells in the other alternate rows retain the original data. Following verification of the updated contents, the original data in the other half-cells are overwritten with the verified updated data, and the operating mode is changed back to the normal (2T2C) operating mode.

公开(公告)号：US20160358640A1

公开(公告)日：2016-12-08

申请号：US15139865

申请日：2016-04-27

Applicant: Texas Instruments Deutschland GmbH ,  Texas Instruments Incorporated

Inventor： Ralf Brederlow ,  Oscar Miguel Guillen-Hernandez ,  Peter Wongeun Chung

IPC: G11C11/22 ,  G06F9/445

CPC classification number: G06F8/65 ,  G11C11/221 ,  G11C11/225 ,  G11C11/2253

Abstract: An integrated circuit including a ferroelectric random access memory (FRAM) for storing firmware, and a method of updating that firmware. The FRAM is constructed to selectively operate as a 2T2C FRAM memory in a normal operating mode, and as a 1T1C FRAM memory in an update mode. Updating of the stored firmware is performed by placing the FRAM in its update (1T1C) mode and writing the updated code into alternate rows of the 1T1C half-cells at each of a plurality of memory locations, while the other 1T1C half-cells in the other alternate rows retain the original data. Following verification of the updated contents, the original data in the other half-cells are overwritten with the verified updated data, and the operating mode is changed back to the normal (2T2C) operating mode.

Abstract translation: 包括用于存储固件的铁电随机存取存储器（FRAM）的集成电路以及更新该固件的方法。 FRAM被构造为在正常操作模式下选择性地作为2T2C FRAM存储器操作，并且作为更新模式中的1T1C FRAM存储器。 存储的固件的更新通过将FRAM置于其更新（1T1C）模式并且将更新的代码写入多个存储器位置中的每一个处的1T1C半单元的交替行而执行，而另一个1T1C半单元 其他替代行保留原始数据。 在更新内容的验证之后，通过验证的更新数据覆盖其他半小区中的原始数据，并且将操作模式改变回正常（2T2C）操作模式。