公开(公告)号：US20230184713A1

公开(公告)日：2023-06-15

申请号：US18066206

申请日：2022-12-14

Applicant: Texas Instruments Incorporated

Inventor： Sebastian Meier ,  Ernst Muellner ,  Helmut Rinck ,  Scott Summerfelt ,  Tobias Fritz ,  Baher Haroun

IPC: G01N27/414

CPC classification number: G01N27/4148 ,  G01N27/4146

Abstract: In some examples, an integrated circuit comprises: a semiconductor die including a semiconductor substrate, a dielectric layer on the semiconductor substrate, and a metallization structure encapsulated in the dielectric layer, in which the semiconductor substrate includes a transistor having a first current terminal, a second current terminal, and a channel region between the first and second current terminals, and the dielectric layer has a sensing side facing away from the semiconductor substrate; an insulation layer on the sensing side; a sensor terminal on the sensing side and over the channel region; and a restriction structure including an opening and a rigid silicon-based fluidic structure, in which the silicon-based fluidic structure is on the sensing side and encapsulates a fluid cavity on the sensing side, the sensor terminal is in the fluid cavity, and the restriction structure is configured to transport a fluid by microfluidic diffusion.

公开(公告)号：US10763833B2

公开(公告)日：2020-09-01

申请号：US16235291

申请日：2018-12-28

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Ernst Gerog Muellner ,  Tobias Fritz ,  Bradley Kramer ,  Swaminathan Sankaran ,  Baher Haroun ,  Ralf Brederlow

IPC: H03K3/03 ,  H03K3/014

Abstract: In described examples, a ring oscillator includes a series of N stages in a first ring. Each stage includes a respective output terminal coupled to a respective input terminal of a next one of the stages in the first ring. N is a positive odd-numbered integer of at least three. A series of N level shifters in a second ring are respectively connected to the N stages. Each level shifter receives a respective clock output from a respective output terminal of a stage to which it is connected and generates a respective boosted clock output in response thereto. The boosted clock output is coupled to control an impedance state of a next one of the level shifters in the second ring.