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公开(公告)号：US11095293B1
公开(公告)日：2021-08-17
申请号：US17139584
申请日：2020-12-31
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Debapriya Sahu , Rittu Sachdev
Abstract: An integrated circuit device is provided. In some examples, the integrated circuit device includes a first re-timer configured to receive a reference clock signal and a voltage controlled oscillator (VCO) output signal, and the first re-timer is configured to provide a first re-timed clock signal in response to the reference clock signal and the VCO output signal. A multiplexer receives the first re-timed clock signal and provides a feedback clock signal. A phase frequency detector receives the feedback clock signal and the reference clock signal and provides an error signal in response to the feedback clock signal and the reference clock signal. A VCO receives a voltage signal based on the error signal, and the VCO is configured to provide the VCO output signal in response to the voltage signal.
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Patent Agency Ranking
公开(公告)号：US12021552B2
公开(公告)日：2024-06-25
申请号：US17566047
申请日：2021-12-30
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Karthik Subburaj , Pranav Sinha , Mayank Kumar Singh , Rittu Sachdev , Karan Singh Bhatia , Shailesh Joshi , Indu Prathapan
CPC classification number: H04B1/0075 , H04B1/04 , H04B1/1036 , H04B1/69 , H04B2001/0408 , H04B2001/1045 , H04B2001/1063 , H04B2001/6912
Abstract: A device comprises a digital ramp generator, an oscillator, a power amplifier, a low-noise amplifier (LNA), a mixer, and an intermediate frequency amplifier (IFA). The oscillator generates a chirp signal based on an output from the digital ramp generator. The power amplifier receives the chirp signal and outputs an amplified chirp signal to a transmitter antenna. The LNA receives a reflected chirp signal from a receiver antenna. The mixer receives output of the LNA and combines it with the chirp signal from the oscillator. The IFA receives the mixer output signal and includes a configurable high-pass filter, which has a first cutoff frequency during a first portion of the chirp signal and a second cutoff frequency during a second portion of the chirp signal. In some implementations, the first cutoff frequency is chosen based on a frequency of a blocker signal introduced by couplings between the transmitter and receiver antennas.
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公开(公告)号：US11418201B2
公开(公告)日：2022-08-16
申请号：US17146510
申请日：2021-01-12
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Debapriya Sahu , Rittu Sachdev
Abstract: A phase-locked loop (PLL) device includes: 1) a detector configured to output an error signal to indicate a phase offset between a feedback clock signal and a reference clock signal; 2) a charge pump coupled to the detector and configured to output a charge pump signal based on the error signal; 3) an integrator with a feedback path, an input node, a reference node, and an output node, wherein the input node is coupled to the charge pump and receives the charge pump signal; 4) a voltage-controlled oscillator (VCO) coupled to the output node of the integrator via a resistor; and 5) a feedforward circuit coupled directly to the detector and configured to apply an averaged version of the error signal to correct a voltage level received by the VCO.
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公开(公告)号：US11777507B2
公开(公告)日：2023-10-03
申请号：US17865808
申请日：2022-07-15
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Debapriya Sahu , Rittu Sachdev
Abstract: A phase-locked loop (PLL) device includes: 1) a detector configured to output an error signal to indicate a phase offset between a feedback clock signal and a reference clock signal; 2) a charge pump coupled to the detector and configured to output a charge pump signal based on the error signal; 3) an integrator with a feedback path, an input node, a reference node, and an output node, wherein the input node is coupled to the charge pump and receives the charge pump signal; 4) a voltage-controlled oscillator (VCO) coupled to the output node of the integrator via a resistor; and 5) a feedforward circuit coupled directly to the detector and configured to apply an averaged version of the error signal to correct a voltage level received by the VCO.
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公开(公告)号：US11303284B1
公开(公告)日：2022-04-12
申请号：US17375997
申请日：2021-07-14
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Debapriya Sahu , Rittu Sachdev
Abstract: An integrated circuit device is provided. In some examples, the integrated circuit device includes a first re-timer configured to receive a reference clock signal and a voltage controlled oscillator (VCO) output signal, and the first re-timer is configured to provide a first re-timed clock signal in response to the reference clock signal and the VCO output signal. A multiplexer receives the first re-timed clock signal and provides a feedback clock signal. A phase frequency detector receives the feedback clock signal and the reference clock signal and provides an error signal in response to the feedback clock signal and the reference clock signal. A VCO receives a voltage signal based on the error signal, and the VCO is configured to provide the VCO output signal in response to the voltage signal.
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公开(公告)号：US10924123B2
公开(公告)日：2021-02-16
申请号：US16219067
申请日：2018-12-13
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Debapriya Sahu , Rittu Sachdev
Abstract: A phase-locked loop (PLL) device includes: 1) a detector configured to output an error signal to indicate a phase offset between a feedback clock signal and a reference clock signal; 2) a charge pump coupled to the detector and configured to output a charge pump signal based on the error signal; 3) an integrator with a feedback path, an input node, a reference node, and an output node, wherein the input node is coupled to the charge pump and receives the charge pump signal; 4) a voltage-controlled oscillator (VCO) coupled to the output node of the integrator via a resistor; and 5) a feedforward circuit coupled directly to the detector and configured to apply an averaged version of the error signal to correct a voltage level received by the VCO.
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