公开(公告)号：US20180226117A1

公开(公告)日：2018-08-09

申请号：US15944666

申请日：2018-04-03

Applicant: Texas Instruments Incorporated

Inventor： Robert C. Baumann ,  John A. Rodriguez

IPC: G11C11/22

Abstract: A system includes a ferroelectric random access memory (FRAM) array having one or more memory elements. A cycle controller cycles data to be fixed in a subset of the one or more memory elements by reading or writing the data a predetermined number of times to fix the data to a non-volatile stable state.

公开(公告)号：US09934840B2

公开(公告)日：2018-04-03

申请号：US14642375

申请日：2015-03-09

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Robert C. Baumann ,  John A. Rodriguez

IPC: G11C11/22

CPC classification number: G11C11/2275 ,  G11C11/2273

Abstract: A system includes a ferroelectric random access memory (FRAM) array having one or more memory elements. A cycle controller cycles data to be fixed in a subset of the one or more memory elements by reading or writing the data a predetermined number of times to fix the data to a non-volatile stable state.

公开(公告)号：US10546626B2

公开(公告)日：2020-01-28

申请号：US15944666

申请日：2018-04-03

Applicant: Texas Instruments Incorporated

Inventor： Robert C. Baumann ,  John A. Rodriguez

IPC: G11C11/22

Abstract: A system includes a ferroelectric random access memory (FRAM) array having one or more memory elements. A cycle controller cycles data to be fixed in a subset of the one or more memory elements by reading or writing the data a predetermined number of times to fix the data to a non-volatile stable state.

公开(公告)号：US20180188987A1

公开(公告)日：2018-07-05

申请号：US15852618

申请日：2017-12-22

Applicant: Texas Instruments Incorporated

Inventor： John A. Rodriguez ,  Robert C. Baumann ,  Richard A. Bailey

IPC: G06F3/06 ,  G06F7/58 ,  G11C11/22

CPC classification number: G06F3/0623 ,  G06F3/0638 ,  G06F3/0679 ,  G06F7/588 ,  G11C11/221 ,  G11C11/2273 ,  G11C11/2275

Abstract: Disclosed embodiments relate to generating random numbers using two transistor, two capacitor (2T-2C) ferroelectric memory cells. In accordance with one disclosed embodiment, an n-bit random number can be generated by writing to a uniform data pattern to a set of n 2T-2C ferroelectric memory cells in a 1T-1C mode so that all ferroelectric capacitors of the n 2T-2C cells have a polarization state corresponding to the same data value (e.g., all 0's or all 1's). The n 2T-2C cells are then read in a 2T-2C mode, so that a random bit (a 0 or 1) is produced for each cell, resulting in an n-bit random number. The n-bit random number is stored in the n 2T-2C ferroelectric memory cells by a rewrite operation. Such random numbers are useful for many purposes, including security, such as authentication, integrity checking, and encryption, and for identification.