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公开(公告)号：US20180188987A1
公开(公告)日：2018-07-05
申请号：US15852618
申请日：2017-12-22
Applicant: Texas Instruments Incorporated
Inventor： John A. Rodriguez , Robert C. Baumann , Richard A. Bailey
CPC classification number: G06F3/0623 , G06F3/0638 , G06F3/0679 , G06F7/588 , G11C11/221 , G11C11/2273 , G11C11/2275
Abstract: Disclosed embodiments relate to generating random numbers using two transistor, two capacitor (2T-2C) ferroelectric memory cells. In accordance with one disclosed embodiment, an n-bit random number can be generated by writing to a uniform data pattern to a set of n 2T-2C ferroelectric memory cells in a 1T-1C mode so that all ferroelectric capacitors of the n 2T-2C cells have a polarization state corresponding to the same data value (e.g., all 0's or all 1's). The n 2T-2C cells are then read in a 2T-2C mode, so that a random bit (a 0 or 1) is produced for each cell, resulting in an n-bit random number. The n-bit random number is stored in the n 2T-2C ferroelectric memory cells by a rewrite operation. Such random numbers are useful for many purposes, including security, such as authentication, integrity checking, and encryption, and for identification.
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公开(公告)号：US09842662B2
公开(公告)日：2017-12-12
申请号：US14857873
申请日：2015-09-18
Applicant: Texas Instruments Incorporated
Inventor： Carl Z. Zhou , John A. Rodriguez , Richard A. Bailey
CPC classification number: G11C29/50016 , G11C11/2275 , G11C29/50008
Abstract: A data retention reliability screen of integrated circuits including ferroelectric random access memory (FRAM) arrays. Sampled groups of cells in the FRAM array are tested at various reference voltage levels, after programming to a high polarization capacitance data state and a relaxation time at an elevated temperature. Fail bit counts of the sample groups at the various reference voltage levels are used to derive a test reference voltage, against which all of the FRAM cells in the integrated circuit are then tested after preconditioning (i.e., programming) and another relaxation interval at the elevated temperature, to determine those cells in the integrated circuit that are vulnerable to long-term data retention failure.
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Patent Agency Ranking
公开(公告)号：US20160240269A1
公开(公告)日：2016-08-18
申请号：US14857873
申请日：2015-09-18
Applicant: Texas Instruments Incorporated
Inventor： Carl Z. Zhou , John A. Rodriguez , Richard A. Bailey
CPC classification number: G11C29/50016 , G11C11/2275 , G11C29/50008
Abstract: A data retention reliability screen of integrated circuits including ferroelectric random access memory (FRAM) arrays. Sampled groups of cells in the FRAM array are tested at various reference voltage levels, after programming to a high polarization capacitance data state and a relaxation time at an elevated temperature. Fail bit counts of the sample groups at the various reference voltage levels are used to derive a test reference voltage, against which all of the FRAM cells in the integrated circuit are then tested after preconditioning (i.e., programming) and another relaxation interval at the elevated temperature, to determine those cells in the integrated circuit that are vulnerable to long-term data retention failure.
Abstract translation: 包括铁电随机存取存储器（FRAM）阵列的集成电路的数据保留可靠性屏幕。 在编程到高极化电容数据状态和升高温度下的弛豫时间之后，以各种参考电压电平测试FRAM阵列中的采样组的单元。 使用各种参考电压电平下的采样组的故障位计数来导出测试参考电压，然后在预处理（即编程）之后测试集成电路中的所有FRAM单元，并在升高的其他弛豫区间 以确定集成电路中易受长期数据保留故障影响的单元。
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公开(公告)号：US20160240253A1
公开(公告)日：2016-08-18
申请号：US15019698
申请日：2016-02-09
Applicant: Texas Instruments Incorporated
Inventor： Carl Z. Zhou , John A. Rodriguez , Richard A. Bailey
CPC classification number: G11C14/0072 , G11C11/221 , G11C11/2273 , G11C29/50016 , G11C29/70
Abstract: A reliability screen of integrated circuits including ferroelectric random access memory (FRAM) arrays for stuck bits. The FRAM devices are subjected to a high temperature bake in wafer form. A “shmoo” of the reference voltage is performed, at an elevated temperature, for each device to identify a first reference voltage at which a first cell in the device fails a read of its low polarization capacitance data state, and a second reference voltage at which a selected number of cells in the device fail the read. The slope of the line between the first and second reference voltages, in the cumulative fail bit count versus reference voltage plane, is compared with a slope limit to determine whether any stuck bits are present in the device.
Abstract translation: 集成电路的可靠性屏幕，包括用于卡住位的铁电随机存取存储器（FRAM）阵列。 对FRAM器件进行晶片形式的高温烘烤。 在升高的温度下，对于每个器件执行参考电压的“shmoo”，以识别第一参考电压，在该第一参考电压下，器件中的第一单元不能读取其低极化电容数据状态，第二参考电压 设备中选定数量的单元格读取失败。 将累积故障位计数与参考电压平面中的第一和第二参考电压之间的线的斜率与斜率限制进行比较，以确定器件中是否存在任何卡位。
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公开(公告)号：US10290362B2
公开(公告)日：2019-05-14
申请号：US15837451
申请日：2017-12-11
Applicant: Texas Instruments Incorporated
Inventor： Carl Z. Zhou , John A. Rodriguez , Richard A. Bailey
Abstract: A data retention reliability screen of integrated circuits including ferroelectric random access memory (FRAM) arrays. Sampled groups of cells in the FRAM array are tested at various reference voltage levels, after programming to a high polarization capacitance data state and a relaxation time at an elevated temperature. Fail bit counts of the sample groups at the various reference voltage levels are used to derive a test reference voltage, against which all of the FRAM cells in the integrated circuit are then tested after preconditioning (i.e., programming) and another relaxation interval at the elevated temperature, to determine those cells in the integrated circuit that are vulnerable to long-term data retention failure.
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公开(公告)号：US20180102184A1
公开(公告)日：2018-04-12
申请号：US15837451
申请日：2017-12-11
Applicant: Texas Instruments Incorporated
Inventor： Carl Z. Zhou , John A. Rodriguez , Richard A. Bailey
CPC classification number: G11C29/50016 , G11C11/2275 , G11C29/50008
Abstract: A data retention reliability screen of integrated circuits including ferroelectric random access memory (FRAM) arrays. Sampled groups of cells in the FRAM array are tested at various reference voltage levels, after programming to a high polarization capacitance data state and a relaxation time at an elevated temperature. Fail bit counts of the sample groups at the various reference voltage levels are used to derive a test reference voltage, against which all of the FRAM cells in the integrated circuit are then tested after preconditioning (i.e., programming) and another relaxation interval at the elevated temperature, to determine those cells in the integrated circuit that are vulnerable to long-term data retention failure.
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公开(公告)号：US09552880B2
公开(公告)日：2017-01-24
申请号：US15019698
申请日：2016-02-09
Applicant: Texas Instruments Incorporated
Inventor： Carl Z. Zhou , John A. Rodriguez , Richard A. Bailey
CPC classification number: G11C14/0072 , G11C11/221 , G11C11/2273 , G11C29/50016 , G11C29/70
Abstract: A reliability screen of integrated circuits including ferroelectric random access memory (FRAM) arrays for stuck bits. The FRAM devices are subjected to a high temperature bake in wafer form. A “shmoo” of the reference voltage is performed, at an elevated temperature, for each device to identify a first reference voltage at which a first cell in the device fails a read of its low polarization capacitance data state, and a second reference voltage at which a selected number of cells in the device fail the read. The slope of the line between the first and second reference voltages, in the cumulative fail bit count versus reference voltage plane, is compared with a slope limit to determine whether any stuck bits are present in the device.
Abstract translation: 集成电路的可靠性屏幕，包括用于卡住位的铁电随机存取存储器（FRAM）阵列。 对FRAM器件进行晶片形式的高温烘烤。 在升高的温度下，对于每个器件执行参考电压的“shmoo”，以识别第一参考电压，在该第一参考电压下，器件中的第一单元不能读取其低极化电容数据状态，第二参考电压 设备中选定数量的单元格读取失败。 将累积故障位计数与参考电压平面中的第一和第二参考电压之间的线的斜率与斜率限制进行比较，以确定器件中是否存在任何卡位。
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