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    Screening for data retention loss in ferroelectric memories
    1.
    发明授权
    Screening for data retention loss in ferroelectric memories 有权

    公开(公告)号：US09842662B2

    公开(公告)日：2017-12-12

    申请号：US14857873

    申请日：2015-09-18

    Applicant: Texas Instruments Incorporated

    Inventor： Carl Z. Zhou ,  John A. Rodriguez ,  Richard A. Bailey

    IPC: G11C29/50 ,  G11C11/22

    CPC classification number: G11C29/50016 ,  G11C11/2275 ,  G11C29/50008

    Abstract: A data retention reliability screen of integrated circuits including ferroelectric random access memory (FRAM) arrays. Sampled groups of cells in the FRAM array are tested at various reference voltage levels, after programming to a high polarization capacitance data state and a relaxation time at an elevated temperature. Fail bit counts of the sample groups at the various reference voltage levels are used to derive a test reference voltage, against which all of the FRAM cells in the integrated circuit are then tested after preconditioning (i.e., programming) and another relaxation interval at the elevated temperature, to determine those cells in the integrated circuit that are vulnerable to long-term data retention failure.

    Screening for Data Retention Loss in Ferroelectric Memories
    2.
    发明申请
    Screening for Data Retention Loss in Ferroelectric Memories 有权
    铁电存储器中数据保留损耗的筛选

    公开(公告)号：US20160240269A1

    公开(公告)日：2016-08-18

    申请号：US14857873

    申请日：2015-09-18

    Applicant: Texas Instruments Incorporated

    Inventor： Carl Z. Zhou ,  John A. Rodriguez ,  Richard A. Bailey

    IPC: G11C29/50 ,  G11C11/22

    CPC classification number: G11C29/50016 ,  G11C11/2275 ,  G11C29/50008

    Abstract: A data retention reliability screen of integrated circuits including ferroelectric random access memory (FRAM) arrays. Sampled groups of cells in the FRAM array are tested at various reference voltage levels, after programming to a high polarization capacitance data state and a relaxation time at an elevated temperature. Fail bit counts of the sample groups at the various reference voltage levels are used to derive a test reference voltage, against which all of the FRAM cells in the integrated circuit are then tested after preconditioning (i.e., programming) and another relaxation interval at the elevated temperature, to determine those cells in the integrated circuit that are vulnerable to long-term data retention failure.

    Abstract translation: 包括铁电随机存取存储器（FRAM）阵列的集成电路的数据保留可靠性屏幕。 在编程到高极化电容数据状态和升高温度下的弛豫时间之后，以各种参考电压电平测试FRAM阵列中的采样组的单元。 使用各种参考电压电平下的采样组的故障位计数来导出测试参考电压，然后在预处理（即编程）之后测试集成电路中的所有FRAM单元，并在升高的其他弛豫区间 以确定集成电路中易受长期数据保留故障影响的单元。

    Screening for Later Life Stuck Bits in Ferroelectric Memories
    3.
    发明申请
    Screening for Later Life Stuck Bits in Ferroelectric Memories 有权
    筛选铁电记忆中的后期生活扣留位

    公开(公告)号：US20160240253A1

    公开(公告)日：2016-08-18

    申请号：US15019698

    申请日：2016-02-09

    Applicant: Texas Instruments Incorporated

    Inventor： Carl Z. Zhou ,  John A. Rodriguez ,  Richard A. Bailey

    IPC: G11C14/00 ,  G11C11/22

    CPC classification number: G11C14/0072 ,  G11C11/221 ,  G11C11/2273 ,  G11C29/50016 ,  G11C29/70

    Abstract: A reliability screen of integrated circuits including ferroelectric random access memory (FRAM) arrays for stuck bits. The FRAM devices are subjected to a high temperature bake in wafer form. A “shmoo” of the reference voltage is performed, at an elevated temperature, for each device to identify a first reference voltage at which a first cell in the device fails a read of its low polarization capacitance data state, and a second reference voltage at which a selected number of cells in the device fail the read. The slope of the line between the first and second reference voltages, in the cumulative fail bit count versus reference voltage plane, is compared with a slope limit to determine whether any stuck bits are present in the device.

    Abstract translation: 集成电路的可靠性屏幕，包括用于卡住位的铁电随机存取存储器（FRAM）阵列。 对FRAM器件进行晶片形式的高温烘烤。 在升高的温度下，对于每个器件执行参考电压的“shmoo”，以识别第一参考电压，在该第一参考电压下，器件中的第一单元不能读取其低极化电容数据状态，第二参考电压 设备中选定数量的单元格读取失败。 将累积故障位计数与参考电压平面中的第一和第二参考电压之间的线的斜率与斜率限制进行比较，以确定器件中是否存在任何卡位。

    Reliability screening of ferroelectric memories in integrated circuits
    7.
    发明授权
    Reliability screening of ferroelectric memories in integrated circuits 有权

    公开(公告)号：US09607717B2

    公开(公告)日：2017-03-28

    申请号：US14519894

    申请日：2014-10-21

    Applicant: Texas Instruments Incorporated

    Inventor： Richard Bailey ,  John A. Rodriguez

    IPC: G11C29/50 ,  G11C11/22

    CPC classification number: G11C29/50016 ,  G11C11/225

    Abstract: A data retention reliability screen of integrated circuits including ferroelectric random access memory (FRAM) arrays. A reference voltage level is determined for each integrated circuit being tested, corresponding to the read of a high polarization capacitance data state. A number of FRAM cells in the integrated circuit are programmed to that data state, and then read at an elevated temperature, with the number of failing cells compared against a pass/fail threshold to determine whether the integrated circuit is vulnerable to long-term data retention failure.

    Setting of Reference Voltage for Data Sensing in Ferroelectric Memories
    8.
    发明申请
    Setting of Reference Voltage for Data Sensing in Ferroelectric Memories 有权
    铁电存储器中数据传感参考电压的设定

    公开(公告)号：US20160240238A1

    公开(公告)日：2016-08-18

    申请号：US15019026

    申请日：2016-02-09

    Applicant: Texas Instruments Incorporated

    Inventor： Carl Z. Zhou ,  Keith A. Remack ,  John A. Rodriguez

    IPC: G11C11/22

    CPC classification number: G11C11/221 ,  G11C11/2273 ,  G11C11/2275 ,  G11C29/028 ,  G11C29/50 ,  G11C29/50016

    Abstract: A method of setting the reference voltage for sensing data states in integrated circuits including ferroelectric random access memory (FRAM) cells of the one-transistor-one capacitor (1T-1C) type. In an electrical test operation, some or all of the FRAM cells are programmed to a particular polarization state. A “shmoo” of the reference voltage for sensing the data state is performed, at one or more worst case electrical or environmental conditions for that data state, to determine a reference voltage limit at which the weakest cell fails to return the correct data when read. A configuration register is then written with a reference voltage based on this reference voltage limit, for example at the limit plus/minus a tolerance.

    Abstract translation: 一种用于在包括单晶体管一电容器（1T-1C）类型的铁电随机存取存储器（FRAM）单元的集成电路中设置用于感测数据状态的参考电压的方法。 在电测试操作中，部分或全部FRAM单元被编程为特定的偏振状态。 在用于该数据状态的一个或多个最坏情况的电气或环境条件下执行用于感测数据状态的参考电压的“shmoo”，以确定在读取时最弱单元不能返回正确数据的参考电压极限 。 然后，基于该参考电压限制，以参考电压写入配置寄存器，例如在极限加上/减去公差。

    Setting of reference voltage for data sensing in ferroelectric memories
    10.
    发明授权
    Setting of reference voltage for data sensing in ferroelectric memories 有权

    公开(公告)号：US10573367B2

    公开(公告)日：2020-02-25

    申请号：US15678357

    申请日：2017-08-16

    Applicant: Texas Instruments Incorporated

    Inventor： Carl Z. Zhou ,  Keith A. Remack ,  John A. Rodriguez

    IPC: G11C13/00 ,  G11C11/22 ,  G11C29/02 ,  G11C29/50

    Abstract: Disclosed embodiments include a testing system that electrically connects to an integrated circuit (IC) having ferroelectric memory (FRAM) cells. The testing system programs the FRAM cells to a first data state and then iteratively reads the programmed cells at a plurality of reference voltages to identify a reference voltage limit that indicates a first occurrence at which at least one of the cells fails to return the first data state when read. Iteratively reading the cells includes reading each cell at an initial reference voltage at which all the cells return the first data state, and then reading each of the programmed cells at each of the remaining reference voltages by incrementally changing the initial reference voltage in one direction until the reference voltage limit is identified. The testing system sets the reference in the IC at an operating level based on the reference voltage limit.

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