公开(公告)号：US11916067B2

公开(公告)日：2024-02-27

申请号：US17684774

申请日：2022-03-02

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Robert M. Higgins ,  Henry Litzmann Edwards ,  Xiaoju Wu ,  Shariq Arshad ,  Li Wang ,  Jonathan Philip Davis ,  Tathagata Chatterjee

IPC: H01L27/06 ,  H01L29/06 ,  H01L21/8234 ,  H01L21/762 ,  G06F30/392 ,  H01L49/02

CPC classification number: H01L27/0629 ,  G06F30/392 ,  H01L21/762 ,  H01L21/823481 ,  H01L28/20 ,  H01L29/0649

Abstract: The present disclosure introduces, among other things, an electronic device, e.g. an integrated circuit (IC). The IC includes a semiconductor substrate comprising a first doped layer of a first conductivity type. A second doped layer of the first conductivity type is located within the first doped layer. The second doped layer has first and second layer portions with a greater dopant concentration than the first doped layer, with the first layer portion being spaced apart from the second layer portion laterally with respect to a surface of the substrate. The IC further includes a lightly doped portion of the first doped layer, the lightly doped portion being located between the first and second layer portions. A dielectric isolation structure is located between the first and second layer portions, and directly contacts the lightly doped portion.

公开(公告)号：US20230378005A1

公开(公告)日：2023-11-23

申请号：US17746655

申请日：2022-05-17

Applicant: Texas Instruments Incorporated

Inventor： Honglin Guo ,  Robert M. Higgins

IPC: H01L21/66

CPC classification number: H01L22/34

Abstract: A method of forming an integrated circuit on a substrate is described herein. The method includes forming a first doped region of a detection structure on the substrate, the first doped region comprises a first doped conductivity type. The method forming a capacitor of the detection structure, which includes forming a second doped region of a second conductivity type opposite the first doped conductivity type, the second doped region surrounded by the first doped region. The second doped well comprises a top surface area smaller than a top surface area of the first doped region. The method includes performing parametric testing on the capacitor over a plurality of breakdown voltages. The method includes determining the gate oxide integrity of the capacitor based on the parametric testing over the plurality of breakdown voltages.

公开(公告)号：US20200075583A1

公开(公告)日：2020-03-05

申请号：US16118648

申请日：2018-08-31

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Robert M. Higgins ,  Henry Litzmann Edwards ,  Xiaoju Wu ,  Shariq Arshad ,  Li Wang ,  Jonathan Philip Davis ,  Tathagata Chatterjee

IPC: H01L27/06 ,  H01L29/06 ,  H01L21/762 ,  H01L21/8234 ,  H01L49/02 ,  G06F17/50

Abstract: The present disclosure introduces, among other things, an electronic device, e.g. an integrated circuit (IC). The IC includes a semiconductor substrate comprising a first doped layer of a first conductivity type. A second doped layer of the first conductivity type is located within the first doped layer. The second doped layer has first and second layer portions with a greater dopant concentration than the first doped layer, with the first layer portion being spaced apart from the second layer portion laterally with respect to a surface of the substrate. The IC further includes a lightly doped portion of the first doped layer, the lightly doped portion being located between the first and second layer portions. A dielectric isolation structure is located between the first and second layer portions, and directly contacts the lightly doped portion.

公开(公告)号：US20220189949A1

公开(公告)日：2022-06-16

申请号：US17684774

申请日：2022-03-02

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Robert M. Higgins ,  Henry Litzmann Edwards ,  Xiaoju Wu ,  Shariq Arshad ,  Li Wang ,  Jonathan Philip Davis ,  Tathagata Chatterjee

IPC: H01L27/06 ,  H01L29/06 ,  H01L21/8234 ,  H01L49/02 ,  H01L21/762 ,  G06F30/392

Abstract: The present disclosure introduces, among other things, an electronic device, e.g. an integrated circuit (IC). The IC includes a semiconductor substrate comprising a first doped layer of a first conductivity type. A second doped layer of the first conductivity type is located within the first doped layer. The second doped layer has first and second layer portions with a greater dopant concentration than the first doped layer, with the first layer portion being spaced apart from the second layer portion laterally with respect to a surface of the substrate. The IC further includes a lightly doped portion of the first doped layer, the lightly doped portion being located between the first and second layer portions. A dielectric isolation structure is located between the first and second layer portions, and directly contacts the lightly doped portion.

公开(公告)号：US11296075B2

公开(公告)日：2022-04-05

申请号：US16118648

申请日：2018-08-31

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Robert M. Higgins ,  Henry Litzmann Edwards ,  Xiaoju Wu ,  Shariq Arshad ,  Li Wang ,  Jonathan Philip Davis ,  Tathagata Chatterjee

IPC: H01L27/06 ,  H01L29/06 ,  H01L21/8234 ,  H01L49/02 ,  H01L21/762 ,  G06F30/392

Abstract: The present disclosure introduces, among other things, an electronic device, e.g. an integrated circuit (IC). The IC includes a semiconductor substrate comprising a first doped layer of a first conductivity type. A second doped layer of the first conductivity type is located within the first doped layer. The second doped layer has first and second layer portions with a greater dopant concentration than the first doped layer, with the first layer portion being spaced apart from the second layer portion laterally with respect to a surface of the substrate. The IC further includes a lightly doped portion of the first doped layer, the lightly doped portion being located between the first and second layer portions. A dielectric isolation structure is located between the first and second layer portions, and directly contacts the lightly doped portion.