公开(公告)号：US20200075583A1

公开(公告)日：2020-03-05

申请号：US16118648

申请日：2018-08-31

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Robert M. Higgins ,  Henry Litzmann Edwards ,  Xiaoju Wu ,  Shariq Arshad ,  Li Wang ,  Jonathan Philip Davis ,  Tathagata Chatterjee

IPC: H01L27/06 ,  H01L29/06 ,  H01L21/762 ,  H01L21/8234 ,  H01L49/02 ,  G06F17/50

Abstract: The present disclosure introduces, among other things, an electronic device, e.g. an integrated circuit (IC). The IC includes a semiconductor substrate comprising a first doped layer of a first conductivity type. A second doped layer of the first conductivity type is located within the first doped layer. The second doped layer has first and second layer portions with a greater dopant concentration than the first doped layer, with the first layer portion being spaced apart from the second layer portion laterally with respect to a surface of the substrate. The IC further includes a lightly doped portion of the first doped layer, the lightly doped portion being located between the first and second layer portions. A dielectric isolation structure is located between the first and second layer portions, and directly contacts the lightly doped portion.

公开(公告)号：US12159846B2

公开(公告)日：2024-12-03

申请号：US16707917

申请日：2019-12-09

Applicant: Texas Instruments Incorporated

Inventor： Richard Allen Faust ,  Robert Martin Higgins ,  Anagha Shashishekhar Kulkarni ,  Jonathan Philip Davis ,  Sudtida Lavangkul ,  Andrew Frank Burnett

IPC: H01L23/00 ,  H01L21/8234

Abstract: A method of forming a semiconductor device for improving an electrical connection. The semiconductor device includes a top metal layer. A protective dielectric layer is formed over the top metal layer. A sintering operation is performed while the top metal layer is covered by the protective dielectric layer. After the sintering operation, the protective dielectric layer is patterned to expose areas on the top metal layer for bond pads of the semiconductor device. A bond pad cap is formed on the top metal layer where exposed by the protective dielectric layer.

公开(公告)号：US11296075B2

公开(公告)日：2022-04-05

申请号：US16118648

申请日：2018-08-31

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Robert M. Higgins ,  Henry Litzmann Edwards ,  Xiaoju Wu ,  Shariq Arshad ,  Li Wang ,  Jonathan Philip Davis ,  Tathagata Chatterjee

IPC: H01L27/06 ,  H01L29/06 ,  H01L21/8234 ,  H01L49/02 ,  H01L21/762 ,  G06F30/392

Abstract: The present disclosure introduces, among other things, an electronic device, e.g. an integrated circuit (IC). The IC includes a semiconductor substrate comprising a first doped layer of a first conductivity type. A second doped layer of the first conductivity type is located within the first doped layer. The second doped layer has first and second layer portions with a greater dopant concentration than the first doped layer, with the first layer portion being spaced apart from the second layer portion laterally with respect to a surface of the substrate. The IC further includes a lightly doped portion of the first doped layer, the lightly doped portion being located between the first and second layer portions. A dielectric isolation structure is located between the first and second layer portions, and directly contacts the lightly doped portion.

公开(公告)号：US11171035B2

公开(公告)日：2021-11-09

申请号：US16567661

申请日：2019-09-11

Applicant: Texas Instruments Incorporated

Inventor： Karen Hildegard Ralston Kirmse ,  Jonathan Philip Davis

IPC: H01L21/762 ,  H01L29/06 ,  H01L21/311 ,  H01L21/308 ,  H01L21/3065

Abstract: Techniques of fabricating shallow trench isolation structures that reduce or minimize the number of trench cones during the formation of shallow trenches. The disclosed techniques introduce separate etch steps for etching shallow trenches with small feature dimensions and for etching shallow trenches with large feature dimensions. As an example, the disclosed techniques involve etching a first shallow trench in a first region of a substrate with a first etching parameter, and etching a second shallow trench in a second region of a substrate with a second etching parameter different from the first etching parameter. Among other things, the etching parameter may include an etching selectivity ratio of silicon to an etch retardant that contributes to cone formations. Because of the separate etch steps, the disclosed techniques allow the sidewall slopes between the first and second shallow trenches to be within a few degrees of deviation.

公开(公告)号：US20240105501A1

公开(公告)日：2024-03-28

申请号：US18530423

申请日：2023-12-06

Applicant: Texas Instruments Incorporated

Inventor： Karen Hildegard Ralston Kirmse ,  Jonathan Philip Davis

IPC: H01L21/762 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/311 ,  H01L29/06

CPC classification number: H01L21/76229 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/31116 ,  H01L29/0649

Abstract: Techniques of fabricating shallow trench isolation structures that reduce or minimize the number of trench cones during the formation of shallow trenches. The disclosed techniques introduce separate etch steps for etching shallow trenches with small feature dimensions and for etching shallow trenches with large feature dimensions. As an example, the disclosed techniques involve etching a first shallow trench in a first region of a substrate with a first etching parameter, and etching a second shallow trench in a second region of a substrate with a second etching parameter different from the first etching parameter. Among other things, the etching parameter may include an etching selectivity ratio of silicon to an etch retardant that contributes to cone formations. Because of the separate etch steps, the disclosed techniques allow the sidewall slopes between the first and second shallow trenches to be within a few degrees of deviation.

公开(公告)号：US11916067B2

公开(公告)日：2024-02-27

申请号：US17684774

申请日：2022-03-02

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Robert M. Higgins ,  Henry Litzmann Edwards ,  Xiaoju Wu ,  Shariq Arshad ,  Li Wang ,  Jonathan Philip Davis ,  Tathagata Chatterjee

IPC: H01L27/06 ,  H01L29/06 ,  H01L21/8234 ,  H01L21/762 ,  G06F30/392 ,  H01L49/02

CPC classification number: H01L27/0629 ,  G06F30/392 ,  H01L21/762 ,  H01L21/823481 ,  H01L28/20 ,  H01L29/0649

Abstract: The present disclosure introduces, among other things, an electronic device, e.g. an integrated circuit (IC). The IC includes a semiconductor substrate comprising a first doped layer of a first conductivity type. A second doped layer of the first conductivity type is located within the first doped layer. The second doped layer has first and second layer portions with a greater dopant concentration than the first doped layer, with the first layer portion being spaced apart from the second layer portion laterally with respect to a surface of the substrate. The IC further includes a lightly doped portion of the first doped layer, the lightly doped portion being located between the first and second layer portions. A dielectric isolation structure is located between the first and second layer portions, and directly contacts the lightly doped portion.

公开(公告)号：US11908729B2

公开(公告)日：2024-02-20

申请号：US17478306

申请日：2021-09-17

Applicant: Texas Instruments Incorporated

Inventor： Karen Hildegard Ralston Kirmse ,  Jonathan Philip Davis

IPC: H01L21/762 ,  H01L29/06 ,  H01L21/311 ,  H01L21/308 ,  H01L21/3065

CPC classification number: H01L21/76229 ,  H01L21/308 ,  H01L21/3065 ,  H01L21/31116 ,  H01L29/0649

Abstract: Techniques of fabricating shallow trench isolation structures that reduce or minimize the number of trench cones during the formation of shallow trenches. The disclosed techniques introduce separate etch steps for etching shallow trenches with small feature dimensions and for etching shallow trenches with large feature dimensions. As an example, the disclosed techniques involve etching a first shallow trench in a first region of a substrate with a first etching parameter, and etching a second shallow trench in a second region of a substrate with a second etching parameter different from the first etching parameter. Among other things, the etching parameter may include an etching selectivity ratio of silicon to an etch retardant that contributes to cone formations. Because of the separate etch steps, the disclosed techniques allow the sidewall slopes between the first and second shallow trenches to be within a few degrees of deviation.

公开(公告)号：US20220005729A1

公开(公告)日：2022-01-06

申请号：US17478306

申请日：2021-09-17

Applicant: Texas Instruments Incorporated

Inventor： Karen Hildegard Ralston Kirmse ,  Jonathan Philip Davis

IPC: H01L21/762 ,  H01L29/06 ,  H01L21/311 ,  H01L21/308 ,  H01L21/3065

Abstract: Techniques of fabricating shallow trench isolation structures that reduce or minimize the number of trench cones during the formation of shallow trenches. The disclosed techniques introduce separate etch steps for etching shallow trenches with small feature dimensions and for etching shallow trenches with large feature dimensions. As an example, the disclosed techniques involve etching a first shallow trench in a first region of a substrate with a first etching parameter, and etching a second shallow trench in a second region of a substrate with a second etching parameter different from the first etching parameter. Among other things, the etching parameter may include an etching selectivity ratio of silicon to an etch retardant that contributes to cone formations. Because of the separate etch steps, the disclosed techniques allow the sidewall slopes between the first and second shallow trenches to be within a few degrees of deviation.

公开(公告)号：US20210005560A1

公开(公告)日：2021-01-07

申请号：US16707917

申请日：2019-12-09

Applicant: Texas Instruments Incorporated

Inventor： Richard Allen Faust ,  Robert Martin Higgins ,  Anagha Shashishekhar Kulkarni ,  Jonathan Philip Davis ,  Sudtida Lavangkul ,  Andrew Frank Burnett

IPC: H01L23/00 ,  H01L21/8234

Abstract: A method of forming a semiconductor device for improving an electrical connection. The semiconductor device includes a top metal layer. A protective dielectric layer is formed over the top metal layer. A sintering operation is performed while the top metal layer is covered by the protective dielectric layer. After the sintering operation, the protective dielectric layer is patterned to expose areas on the top metal layer for bond pads of the semiconductor device. A bond pad cap is formed on the top metal layer where exposed by the protective dielectric layer.

公开(公告)号：US20190198382A1

公开(公告)日：2019-06-27

申请号：US15852171

申请日：2017-12-22

Applicant: Texas Instruments Incorporated

Inventor： Karen Hildegard Ralston Kirmse ,  Jonathan Philip Davis

IPC: H01L21/762 ,  H01L29/06 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/311

Abstract: Techniques of fabricating shallow trench isolation structures that reduce or minimize the number of trench cones during the formation of shallow trenches. The disclosed techniques introduce separate etch steps for etching shallow trenches with small feature dimensions and for etching shallow trenches with large feature dimensions. As an example, the disclosed techniques involve etching a first shallow trench in a first region of a substrate with a first etching parameter, and etching a second shallow trench in a second region of a substrate with a second etching parameter different from the first etching parameter. Among other things, the etching parameter may include an etching selectivity ratio of silicon to an etch retardant that contributes to cone formations. Because of the separate etch steps, the disclosed techniques allow the sidewall slopes between the first and second shallow trenches to be within a few degrees of deviation.