公开(公告)号：US20220082608A1

公开(公告)日：2022-03-17

申请号：US17537007

申请日：2021-11-29

申请人： TEXAS INSTRUMENTS INCORPORATED

发明人： Yuguo Wang ,  Steven Loveless ,  Tathagata Chatterjee ,  Jerry Doorenbos

IPC分类号： G01R31/26

摘要： A system comprises a noise generator circuit and a noise envelope detector circuit. The noise generator circuit comprises a first amplifier including a single transistor pair that is operable to generate 1/f noise, an output amplifier coupled to the first amplifier and configured to generate a 1/f noise signal as a function of the 1/f noise. The noise envelope detector circuit comprises a low pass filter operable to pass low frequency signals of the 1/f noise signal as a filtered 1/f noise signal, and a second amplifier or a comparator coupled to the low pass filter and operable to output a direct current (DC) voltage signal according to an envelope of the filtered 1/f noise signal, where the DC voltage signal is a function of an envelope of the filtered 1/f noise signal.

公开(公告)号：US10236900B1

公开(公告)日：2019-03-19

申请号：US15836976

申请日：2017-12-11

申请人： TEXAS INSTRUMENTS INCORPORATED

发明人： Steven John Loveless ,  Yuguo Wang ,  Tathagata Chatterjee ,  Robert Stanley Grondalski

IPC分类号： H03K5/24 ,  H03M1/10 ,  G01R27/26 ,  H03K21/08

摘要： An analog-to-digital converter (ADC) comprising successive approximation circuitry, a capacitive analog-to-digital converter (CDAC), and capacitor mismatch measurement circuitry. The successive approximation circuitry is configured to control conversion of an analog signal to a digital value. The CDAC is coupled to the successive approximation circuitry. The CDAC includes a plurality of capacitors. The capacitor mismatch measurement circuitry is coupled to the CDAC. The capacitor mismatch measurement circuitry includes a first oscillator circuit, a second oscillator circuit, and counter circuitry. The first oscillator circuit is configured to oscillate at a frequency determined by a capacitance of one of the capacitors. The second oscillator circuit is configured to generate a predetermined time interval. The counter circuitry is configured to count a number of cycles of oscillation of the first oscillator in the predetermined time interval.

公开(公告)号：US11296075B2

公开(公告)日：2022-04-05

申请号：US16118648

申请日：2018-08-31

申请人： TEXAS INSTRUMENTS INCORPORATED

发明人： Robert M. Higgins ,  Henry Litzmann Edwards ,  Xiaoju Wu ,  Shariq Arshad ,  Li Wang ,  Jonathan Philip Davis ,  Tathagata Chatterjee

IPC分类号： H01L27/06 ,  H01L29/06 ,  H01L21/8234 ,  H01L49/02 ,  H01L21/762 ,  G06F30/392

摘要： The present disclosure introduces, among other things, an electronic device, e.g. an integrated circuit (IC). The IC includes a semiconductor substrate comprising a first doped layer of a first conductivity type. A second doped layer of the first conductivity type is located within the first doped layer. The second doped layer has first and second layer portions with a greater dopant concentration than the first doped layer, with the first layer portion being spaced apart from the second layer portion laterally with respect to a surface of the substrate. The IC further includes a lightly doped portion of the first doped layer, the lightly doped portion being located between the first and second layer portions. A dielectric isolation structure is located between the first and second layer portions, and directly contacts the lightly doped portion.

公开(公告)号：US20200075583A1

公开(公告)日：2020-03-05

申请号：US16118648

申请日：2018-08-31

申请人： TEXAS INSTRUMENTS INCORPORATED

发明人： Robert M. Higgins ,  Henry Litzmann Edwards ,  Xiaoju Wu ,  Shariq Arshad ,  Li Wang ,  Jonathan Philip Davis ,  Tathagata Chatterjee

IPC分类号： H01L27/06 ,  H01L29/06 ,  H01L21/762 ,  H01L21/8234 ,  H01L49/02 ,  G06F17/50

摘要： The present disclosure introduces, among other things, an electronic device, e.g. an integrated circuit (IC). The IC includes a semiconductor substrate comprising a first doped layer of a first conductivity type. A second doped layer of the first conductivity type is located within the first doped layer. The second doped layer has first and second layer portions with a greater dopant concentration than the first doped layer, with the first layer portion being spaced apart from the second layer portion laterally with respect to a surface of the substrate. The IC further includes a lightly doped portion of the first doped layer, the lightly doped portion being located between the first and second layer portions. A dielectric isolation structure is located between the first and second layer portions, and directly contacts the lightly doped portion.

公开(公告)号：US10101382B2

公开(公告)日：2018-10-16

申请号：US15395907

申请日：2016-12-30

申请人： TEXAS INSTRUMENTS INCORPORATED

发明人： Alex Paikin ,  Colin Johnson ,  Tathagata Chatterjee ,  Sameer Pendharkar

IPC分类号： G01R31/10 ,  G01R31/26 ,  G01R31/28

摘要： In at least some embodiments, a system comprises a socket gate terminal configured to receive a first voltage to activate and inactivate a device under test (DUT) coupled to the socket gate terminal. The system also comprises a socket source terminal configured to provide a reference voltage to the DUT. The system further comprises a socket drain terminal configured to provide a second voltage to the DUT to stress the DUT when the DUT is inactive. The socket drain terminal is further configured to receive a third voltage to cause a current to flow through a pathway in the DUT between the socket drain terminal and the socket source terminal when the DUT is active. The socket drain terminal is further configured to provide a fourth voltage indicative of a resistance of the pathway in the DUT when the DUT is active and is heated to a temperature above an ambient temperature associated with the system.

公开(公告)号：US09818740B2

公开(公告)日：2017-11-14

申请号：US15368958

申请日：2016-12-05

申请人： Texas Instruments Incorporated

发明人： Weidong Tian ,  YuGuo Wang ,  Tathagata Chatterjee ,  Rajni J. Aggarwal

IPC分类号： H01L27/06 ,  H01L29/739 ,  H01L29/06 ,  H01L29/10 ,  H01L29/45 ,  H01L29/417 ,  H01L21/8249 ,  H01L27/092

CPC分类号： H01L27/0623 ,  H01L21/8249 ,  H01L27/092 ,  H01L29/0688 ,  H01L29/1004 ,  H01L29/41708 ,  H01L29/423 ,  H01L29/456 ,  H01L29/66272 ,  H01L29/732 ,  H01L29/7395

摘要： An integrated circuit includes an NMOS transistor, a PMOS transistor and a vertical bipolar transistor. The vertical bipolar transistor has an intrinsic base with a band barrier at least 25 meV high at a surface boundary of the intrinsic base, except at an emitter-base junction with an emitter, and except at a base-collector junction with a collector. The intrinsic base may be laterally surrounded by an extrinsic base with a higher dopant density than the intrinsic base, wherein a higher dopant density provides the band barrier at lateral surfaces of the intrinsic base. A gate may be disposed on a gate dielectric layer over a top surface boundary of the intrinsic base adjacent to the emitter. The gate is configured to accumulate the intrinsic base immediately under the gate dielectric layer, providing the band barrier at the top surface boundary of the intrinsic base.

公开(公告)号：US20130255741A1

公开(公告)日：2013-10-03

申请号：US13798878

申请日：2013-03-13

申请人： TEXAS INSTRUMENTS INCORPORATED

发明人： Henry L. Edwards ,  Richard B. Irwin ,  Tathagata Chatterjee

IPC分类号： H01L35/30 ,  H01L35/34

CPC分类号： H01L35/30 ,  H01L23/345 ,  H01L23/38 ,  H01L27/16 ,  H01L35/34 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit with an embedded heat exchanger for coupling heat to an embedded thermoelectric device from a thermal source that is electrically isolated from a thermoelectric device. A method for forming an integrated circuit with an embedded heat exchanger.

摘要翻译： 一种具有嵌入式热交换器的集成电路，用于将热量从与热电装置电隔离的热源耦合到嵌入式热电装置。 一种用嵌入式热交换器形成集成电路的方法。

公开(公告)号：US11916067B2

公开(公告)日：2024-02-27

申请号：US17684774

申请日：2022-03-02

申请人： TEXAS INSTRUMENTS INCORPORATED

发明人： Robert M. Higgins ,  Henry Litzmann Edwards ,  Xiaoju Wu ,  Shariq Arshad ,  Li Wang ,  Jonathan Philip Davis ,  Tathagata Chatterjee

IPC分类号： H01L27/06 ,  H01L29/06 ,  H01L21/8234 ,  H01L21/762 ,  G06F30/392 ,  H01L49/02

CPC分类号： H01L27/0629 ,  G06F30/392 ,  H01L21/762 ,  H01L21/823481 ,  H01L28/20 ,  H01L29/0649

摘要： The present disclosure introduces, among other things, an electronic device, e.g. an integrated circuit (IC). The IC includes a semiconductor substrate comprising a first doped layer of a first conductivity type. A second doped layer of the first conductivity type is located within the first doped layer. The second doped layer has first and second layer portions with a greater dopant concentration than the first doped layer, with the first layer portion being spaced apart from the second layer portion laterally with respect to a surface of the substrate. The IC further includes a lightly doped portion of the first doped layer, the lightly doped portion being located between the first and second layer portions. A dielectric isolation structure is located between the first and second layer portions, and directly contacts the lightly doped portion.

公开(公告)号：US11796588B2

公开(公告)日：2023-10-24

申请号：US17537007

申请日：2021-11-29

申请人： TEXAS INSTRUMENTS INCORPORATED

发明人： Yuguo Wang ,  Steven Loveless ,  Tathagata Chatterjee ,  Jerry Doorenbos

IPC分类号： G01R31/26

CPC分类号： G01R31/2626

摘要： A system comprises a noise generator circuit and a noise envelope detector circuit. The noise generator circuit comprises a first amplifier including a single transistor pair that is operable to generate 1/f noise, an output amplifier coupled to the first amplifier and configured to generate a 1/f noise signal as a function of the 1/f noise. The noise envelope detector circuit comprises a low pass filter operable to pass low frequency signals of the 1/f noise signal as a filtered 1/f noise signal, and a second amplifier or a comparator coupled to the low pass filter and operable to output a direct current (DC) voltage signal according to an envelope of the filtered 1/f noise signal, where the DC voltage signal is a function of an envelope of the filtered 1/f noise signal.

公开(公告)号：US10748818B2

公开(公告)日：2020-08-18

申请号：US16231243

申请日：2018-12-21

申请人： Texas Instruments Incorporated

发明人： Tathagata Chatterjee ,  Steven Loveless ,  James Robert Todd ,  Andrew Strachan

IPC分类号： H01L49/02 ,  H01L21/8234 ,  H01L21/762 ,  H01L23/528 ,  H01L23/00 ,  H01L23/532

摘要： In various examples, a method and apparatus are provided to achieve dynamic biasing to mitigate electrical stress. Described examples include a device includes a first resistor portion having a first terminal and a second terminal, and a second resistor portion having a third terminal and a fourth terminal. The device also includes a well in a substrate proximate to the first resistor portion and the second resistor portion and an insulating layer between the well and the first resistor portion and the second resistor portion. The device also includes a transistor having a control terminal coupled to the second terminal of the first resistor portion and the third terminal of the second resistor portion, the transistor having a first current-handling terminal coupled to a first voltage and a second current-handling terminal coupled to a current source and to the well.